DS21448N Maxim Integrated Products, DS21448N Datasheet
DS21448N
Specifications of DS21448N
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DS21448N Summary of contents
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... Wireless Base Stations ORDERING INFORMATION PART* TEMP RANGE DS21448 0°C to +70°C DS21448+ 0°C to +70°C DS21448N -40°C to +85°C DS21448N+ -40°C to +85°C DS21448L 0°C to +70°C DS21448L+ 0°C to +70°C DS21448LN -40°C to +85°C DS21448LN+ -40°C to +85°C + Denotes lead-free/RoHS-compliant package. ...
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BLOCK DIAGRAMS ........................................................................................................................ 5 2. PIN DESCRIPTION .......................................................................................................................... 7 3. DETAILED DESCRIPTION ............................................................................................................ 13 3.1 DS21448 DS21Q348 D AND 4. PORT OPERATION ....................................................................................................................... 14 4 ......................................................................................................................... 14 ARDWARE ODE 4 ERIAL ORT PERATION 4.3 ...
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Figure 1-1. Block Diagram .......................................................................................................................... 5 Figure 1-2. Receive Logic Detail ................................................................................................................ 6 Figure 1-3. Transmit Logic Detail ............................................................................................................... 6 Figure 4-1. Serial Port Operation for Read Access ( Mode 1 ......................................................... 16 Figure 4-2. Serial Port Operation ...
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Table 2-A. Bus Interface Selection ............................................................................................................. 7 Table 2-B. Pin Assignments ....................................................................................................................... 7 Table 2-C. Parallel Interface Mode Pin Description.................................................................................... 9 Table 2-D. Serial Interface Mode Pin Description .................................................................................... 10 Table 2-E. Hardware Interface Mode Pin Description .............................................................................. 11 Table ...
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BLOCK DIAGRAMS Figure 1-1. Block Diagram CHANNEL 4 CHANNEL 3 CHANNEL 2 CHANNEL POWER CONNECTIONS RRING RTIP UNFRAMED ALL-ONES INSERTION TRING TTIP MUX (THE SERIAL, PARALLEL, AND HARDWARE INTERFACES BIS0 SERIAL INTERFACE JACLK 2.048MHz TO 1.544MHz ...
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Figure 1-2. Receive Logic Detail FROM ROUTED TO REMOTE ALL BLOCKS LOOPBACK ZERO DETECT 16 ZERO DETECT RIR1.7 RIR1.6 Figure 1-3. Transmit Logic Detail CCR1 CCR3.1 1 BPV MUX INSERT TO REMOTE LOOPBACK 0 ...
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PIN DESCRIPTION The DS21448 can be controlled in parallel port mode, serial port mode, or hardware mode. The bus interface select bits 0 and 1 (BIS0, BIS1) determine the device mode and pin assignments Table 2-A. Bus Interface Selection ...
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PIN BGA LQFP B8 61 B11 94 L9 106 J6 109 H4 122 D6 47 F10 56 L8 112 L7 107 A11 102 L10 103 J5 ...
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Table 2-C. Parallel Interface Mode Pin Description PIN I/O Read Input (Data Strobe). RD and DS are active-low signals active low when in RD (DS) I nonmultiplexed, Motorola mode. See the bus timing diagrams in Section 10. WR ...
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PIN I/O Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of RCLK1–RCLK4 O signal at RTIP and RRING. Transmit Positive Data. Sampled on the falling edge (CCR2 the rising edge TPOS1–TPOS4 I ...
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PIN I/O Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is BPCLK1–BPCLK4 O referenced to RCLK selectable through CCR5.7 and CCR5.6. TTIP1–TTIP4 O Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up transformer ...
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PIN I/O Receive and Transmit Clock Select. Selects which RCLK edge to update RPOS and RNEG and which TCLK edge to sample TPOS and TNEG. CES combines TCES and RCES. CES update RPOS/RNEG on rising edge of ...
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PIN I/O TVSS1–TVSS4 — Transmitter Signal Ground for Transmitter Outputs VSS1–VSS4 — Signal Ground Note 1: G.703 requires an accuracy of ±50ppm for T1 and E1. TR62411 and ANSI specs require ±32ppm accuracy for T1 interfaces. 3. DETAILED DESCRIPTION The ...
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PORT OPERATION 4.1 Hardware Mode The DS21448 supports a hardware configuration mode that allows the user to configure the device by setting levels on the device’s pins. This mode allows the DS21448 configuration without the use of a microprocessor, ...
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Table 4-F. MCLK Selection in Hardware Mode MCLK (MHz) JAMUX 2.048 0 2.048 1 1.544 0 4.2 Serial Port Operation Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS21448 timing is unrelated to ...
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Figure 4-1. Serial Port Operation for Read Access ( Mode 1 ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK) SCLK ...
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Figure 4-4. Serial Port Operation for Read Access ( Mode 4 ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK) OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK) SCLK ...
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Parallel Port Operation The option for either multiplexed bus operation (BIS0 = 0) or nonmultiplexed bus operation (BIS0 = 1) is available when using the parallel interface. The DS21448 can operate with either Intel or Motorola bus timing configurations. ...
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Control Registers CCR1 (00H): Common Control Register 1 (MSB) ETS NRZE NAME POSITION E1/T1 Select ETS CCR1 NRZ Enable 0 = bipolar data at RPOS/RNEG and TPOS/TNEG NRZE CCR1 NRZ data ...
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CCR2 (01H): Common Control Register 2 (MSB) RLPIN — NAME POSITION RCL/LOTC Pin Function Select. Forced to logic 0 in hardware mode. RLPIN CCR2 toggles high during a receive-carrier loss condition 1 = toggles high if TCLK does ...
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CCR3 (02H): Common Control Register 3 (MSB) TUA1 ATUA1 NAME POSITION Transmit Unframed All Ones. The polarity of this bit is set such that the device transmits an all- ones pattern on power-up or device reset. This bit must be ...
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Table 4-I. Receive Sensitivity Settings EGL ETS RECEIVE SENSITIVITY (CCR4.4) (CCR1. (E1) -12 (short haul (E1) -43 (long haul (T1) -30 (limited long haul (T1) -36 (long haul) CCR5 (04H): Common Control ...
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CCR6 (05H): Common Control Register 6 (MSB) LLB RLB ARLBE NAME POSITION Local Loopback. In local loopback, transmit data is looped back to the receive path, passing through the jitter attenuator enabled. Data in the transmit path ...
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The bits in the SR register have the unique ability to initiate a hardware interrupt through the INT output pin. Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin through ...
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Table 5-A. Received Alarm Criteria ALARM E1/T1 RUA1 E1 Fewer than two 0s in two frames (512 bits) Over a 3ms window, five or fewer 0s are RUA1 T1 received. RCL 255 (or 2048) consecutive 0s received E1 (Note 1) ...
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RIR1 (08H): Receive Information Register 1 (MSB) ZD 16ZD NAME POSITION Zero Detect. This bit is set when a string of at least four (ETS = 0) or eight (ETS = 1) ZD RIR1.7 consecutive 0s (regardless of the length ...
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Table 5-B. Receive Level Indication RL3 RL2 RL1 ...
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DIAGNOSTICS 6.1 In-Band Loop-Code Generation and Detection The DS21448 can generate and detect a repeating bit pattern from bits in length. To transmit a pattern, the user loads the pattern into the transmit code ...
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Table 6-A. Transmit Code Length LENGTH SELECTED TC1 TC0 (BITS 6 16/8/4/2/1 Table 6-B. Receive Code Length RUP2/RDN2 RUP1/RDN1 ...
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RUPCD1 (0DH): Receive-Up Code Definition Register 1 (MSB NAME POSITION C7 RUPCD1.7 Receive-Up Code Definition Bit 7. First bit of the repeating pattern. C6 RUPCD1.6 Receive-Up Code Definition Bit 6. A don’t care if a 1-bit length is ...
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Loopbacks 6.2.1 Remote Loopback (RLB) When RLB (CCR6.6) is enabled, the DS21448 is placed into remote loopback. In this loopback, data from the clock/data recovery state machine is looped back to the transmit path, passing through the jitter attenuator ...
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Table 6-C. Definition of Received Errors ERROR Two consecutive marks with the same polarity. Ignores BPVs because of HDB3 and B8ZS zero BPV E1/T1 suppression when CCR2 Typically used with AMI coding (CCR2.3 = 1). ...
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ANALOG INTERFACE 7.1 Receiver The DS21448 contains a digital clock recovery system. The DS21448 couples to the receive twisted pair (or coaxial cable in 75Ω E1 applications) through a 1:1 transformer. See Figure 7-1, Figure 7-2, ...
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TCLK. Also, the waveforms created are independent of the duty cycle of TCLK. The transmitter couples to the transmit-twisted pair (or coaxial cable in some E1 applications) ...
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Table 7-C. Line Build-Out Select for E1 in Register CCR4 (ETS = 0) Using Alternate Transformer Configuration APPLICATION 75Ω normal 120Ω normal 75Ω with high return loss 1 ...
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Figure 7-1. Basic Interface TRANSMIT LINE 2:1 (LARGER WINDING TOWARD THE NETWORK) RECEIVE LINE 1:1 NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE APPLICATIONS, THE R RESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS T (Table ...
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Figure 7-2. Protected Interface Using Internal Receive Termination FUSE S TRANSMIT S LINE S FUSE 2:1 (LARGER WINDING TOWARD THE NETWORK) FUSE S RECEIVE S LINE S FUSE 1:1 NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE ...
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Figure 7-3. Protected Interface Using External Receive Termination FUSE S TRANSMIT S LINE S FUSE 2:1 (LARGER WINDING TOWARD THE NETWORK) FUSE S RECEIVE S LINE S FUSE 1:1 NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE ...
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Figure 7-4. Dual Connector-Protected Interface Using Receive Termination FUSE UNBALANCED S LINE (75Ω) FUSE S S BALANCED LINE S (100Ω/120Ω) FUSE FUSE UNBALANCED S LINE (75Ω) 51.1 FUSE S BALANCED LINE S (100Ω/120Ω) S FUSE NOTE 1: REFER TO APPLICATION ...
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Figure 7-5. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 194ns 219ns -150 -100 - TIME (ns 269ns G.703 TEMPLATE 100 150 ...
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Figure 7-6. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 T1.102/87, T1.403, -0.2 CB 119 (OCT ‘79), AND I.431 TEMPLATE -0.3 -0.4 -0.5 -500 -400 -300 MAXIMUM CURVE UI -0.77 ...
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Figure 7-7. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 7-8. Jitter Attenuation 0 -20 -40 - 62411 (DEC ‘90) DS21448 TOLERANCE ITU-T G.823 10 100 1k FREQUENCY (Hz) TBR12 PROHIBITED AREA PROHIBITED AREA CURVE A E1 ...
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JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS21448 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE contains the following items, which meet the requirements ...
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Figure 8-2. TAP Controller State Diagram Test Logic 1 Reset Run Test/ 0 Idle Capture-DR. Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or ...
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Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and initiates a scan sequence for the instruction register. ...
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EXTEST. This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled through the update-IR state, the parallel outputs of all digital output pins are driven. ...
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Table 8-D. Boundary Scan Control Bits PIN BIT NAME BGA LQFP — A1 124 RTIP1 — — RTIP2 — — RTIP3 — — A10 93 RTIP4 — A11 102 — ...
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PIN BIT NAME BGA LQFP — — — M9 104 TVDD4 Note Dn/ADn are inputs Dn/ADn are outputs. Note INT is an input ...
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AC TIMING PARAMETERS AND DIAGRAMS Table 10-A. AC Characteristics—Multiplexed Parallel Port (BIS0 = 0) = 3.3V ±5 -40°C to +85°C PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High ...
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Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS0 = 0) ALE t ASD RD t ASD WR CS AD0–AD7 Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS0 = ASD R/W AD0–AD7 ...
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Table 10-B. AC Characteristics—Nonmultiplexed Parallel Port (BIS0 = 1) = 3.3V ±5 -40°C to +85°C PARAMETER Setup Time for A0 to A4, Valid to CS Active Setup Time for CS Active to Either RD, WR, ...
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Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS0 = 1) A0–A4 D0– 0ns (MIN) WR Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS0 = 1) A0–A4 D0–D7 R/W CS 0ns (MIN) DS Figure ...
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Table 10-C. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) = 3.3V ±5 -40°C to +85°C PARAMETER Setup Time CS to SCLK Setup Time SDI to SCLK Hold Time SCLK to SDI SCLK High/Low ...
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Table 10-D. AC Characteristics—Receive Side = 3.3V ± 5 =-40°C to +85°C PARAMETER RCLK Period RCLK Pulse Width RCLK Pulse Width Delay RCLK to RPOS, RNEG, PBEO, RBPV Valid Note 1: E1 mode. Note 2: T1 ...
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Table 10-E. AC Characteristics—Transmit Side = 3.3V ±5 -40°C to +85°C PARAMETER TCLK Period TCLK Pulse Width TPOS/TNEG Setup to TCLK Falling or Rising TPOS/TNEG Hold from TCLK Falling or Rising TCLK Rise and Fall ...
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PIN CONFIGURATIONS 11.1 144-Pin TE-PBGA RTIP1 TTIP1 N.C. B N.C. RRING1 TRING1 C N.C. N.C. N.C. D TVSS2 TVDD2 CS2 D3/ E RPOS2 RNEG2 AD3 D1/ F RCLK2 TPOS2 AD1 G TPOS1 RNEG1 PEBO2 WR ...
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LQFP TVSS4 100 TVDD4 TRING4 HRST BIS0 PBTS/RT0 MCLK PBEO1 110 PBEO2 BPCLK4 TCLK4 CS4 /EGL4 VDD1 VDD1 VDD1 VSS1 VSS1 VSS1 120 PBEO3 BPCLK1 PBEO4 RTIP1 RRING1 RCL1/LOTC1 RCLK1 RCL2/LOTC2 Dallas Semiconductor DS21448 ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 12.1 144-Ball TE-PBGA (56-G6020-001 ...
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LQFP (56-G4011-001 ...
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