DS26504LNB2 Maxim Integrated Products, DS26504LNB2 Datasheet - Page 103
DS26504LNB2
Manufacturer Part Number
DS26504LNB2
Description
Network Controller & Processor ICs T1-E1-J1-64kHz Compo 4kHz Composite Clock
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26504L.pdf
(129 pages)
Specifications of DS26504LNB2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS26504 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26504
contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture:
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 17-1. JTAG Functional Block Diagram
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
10k Ω
V
DD
JTDI
10k Ω
V
DD
JTMS
TEST ACCESS PORT
BOUNDRY SCAN
IDENTIFICATION
INSTRUCTION
CONTROLLER
REGISTER
REGISTER
REGISTER
REGISTER
BYPASS
JTCLK
103 of 129
10k Ω
V
DD
JTRST
SELECT
OUTPUT ENABLE
MUX
JTDO
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