LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 60

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.3 (02-23-10)
3.12.4
31:16
14:12
BITS
6:3
15
10
11
9
8
7
2
1
0
Packet TAG. Unique identifier written by the host into the Packet Tag field of the TX command ‘B’
word. This field can be used by the host to correlate TX status words with the associated TX packets.
Error Status (ES). When set, this bit indicates that the Ethernet controller has reported an error. This
bit is the logical OR of bits 11, 10, 9, 8, 2, 1 in this status word.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.
Loss of Carrier. When set, this bit indicates the loss of carrier during transmission.
No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present
during transmission.
Note: During 10/100 Mbps full-duplex transmission, the value of this bit is invalid and should be
Late Collision. When set, indicates that the packet transmission was aborted after the collision
window of 64 bytes.
Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16
collisions while attempting to transmit the current packet.
Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.
Collision Count. This counter indicates the number of collisions that occurred before the packet was
transmitted. It is not valid when excessive collisions (bit 8) is also set.
Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive
deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times
during transmission.
Reserved. This bit is reserved. Always write zero to this bit to guarantee future compatibility.
Deferred. When set, this bit indicates that the current packet transmission was deferred.
TX Status Format
TX status is passed to the host CPU through a separate FIFO mechanism. A status word is returned
for each packet transmitted. Data transmission is suspended if the TX status FIFO becomes full. Data
transmission will resume when the host reads the TX status and there is room in the FIFO for more
“TX Status” data.
The host can optionally choose to not read the TX status. The host can optionally ignore the TX status
by setting the “TX Status Discard Allow Overrun Enable” (TXSAO) bit in the TX Configuration Register
(TX_CFG). If this option is chosen TX status will not be written to the FIFO. Setting this bit high allows
the transmitter to continue operation with a full TX status FIFO. In this mode the status information is
still available in the TX status FIFO, and TX status interrupts still function. In the case of an overrun,
the TXSUSED counter will stay at zero and no further TX status will be written to the TX status FIFO
until the host frees space by reading TX status. If TXSAO is enabled, a TXE error will not be generated
if the TX status FIFO overruns. In this mode the host is responsible for re-synchronizing TX status in
the case of an overrun.
ignored.
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
DATASHEET
DESCRIPTION
60
SMSC LAN89218
Datasheet