LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 139

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
6.5
FIFO_SEL
END_SEL
nCS, nRD
Data Bus
A[2:1]
In this mode the upper address inputs are not decoded, and any burst read of the LAN89218 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN89218. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines. This mode improves performance by allowing an unlimited number of back-to-back read
cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS) or Read
Enable (nRD). When either or both of these control signals go high, they must remain high for the
period specified.
Timing for 16-bit and 32-bit RX Data FIFO Direct PIO Burst Reads is identical with the exception that
D[31:16] are not driven during a 16-bit burst. Note that address lines A[2:1] are still used, and address
bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
RX Data FIFO Direct PIO Burst Reads
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
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Revision 1.3 (02-23-10)
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