WM8350GEB/V Wolfson Microelectronics, WM8350GEB/V Datasheet - Page 207

• Manufacturer Part Number: WM8350GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8350GEB/V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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24.3.7
The first-level AUXADC_INT interrupt comprises several second-level interrupts for the auxiliary ADC
and associated digital comparators. Each of these has a status bit in Register R26 and a mask bit in
Register R34, as defined in Table 148.
R26 (1Ah)
Interrupt
Status 2
R34 (22h)
Interrupt
Status 2 Mask
Table 148 AUXADC Interrupts
24.3.8
The first-level RTC_INT interrupt comprises three second-level interrupts for the Real Time Clock.
Each of these has a status bit in Register R25 and a mask bit in Register R33, as defined in Table
149.
R25 (19h)
Interrupt Status
1
R33 (21h)
Interrupt Status
1 Mask
Table 149 RTC Interrupts
ADDRESS
ADDRESS
AUXADC AND DIGITAL COMPARATOR INTERRUPTS
RTC INTERRUPTS
BIT
8:4
BIT
7:5
8
7
6
5
4
7
6
5
AUXADC_DATARDY_EINT
AUXADC_DCOMP4_EINT
AUXADC_DCOMP3_EINT
AUXADC_DCOMP2_EINT
AUXADC_DCOMP1_EINT
“IM_” + name of respective
bit in R26
RTC_PER_EINT
RTC_SEC_EINT
RTC_ALM_EINT
“IM_” + name of respective
bit in R25
LABEL
LABEL
Auxiliary data ready.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP4 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP3 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP2 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCOMP1 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R34 enables or masks the
corresponding bit in R26. The default
value for these bits is 0 (unmasked).
RTC periodic interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
RTC 1s rollover complete (1Hz tick).
(Rising Edge triggered)
Note: This bit is cleared once read.
RTC alarm signalled.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R33 enables or masks the
corresponding bit in R25. The default
value for these bits is 0 (unmasked).
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
WM8350
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