WM8350GEB/V Wolfson Microelectronics, WM8350GEB/V Datasheet - Page 151

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WM8350GEB/V

Manufacturer Part Number
WM8350GEB/V
Description
Audio CODECs Audio CODEC plus pwr management
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8350GEB/V

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Production Data
w
R173 (ADh) for
ISINKA
R175 (AFh) for
ISINKB
Note: n is either ‘1’ for ISINKA or ‘2’ for ISINKB
Table 97 Configuring Flash Mode for ISINKA and ISINKB
Note that the CSn_DRIVE bits are always reset when exiting the hibernate state, regardless of the
REG_RESET_HIB_MODE bit. If the CSn_DRIVE is enabled in the hibernate state, then it must be
re-enabled by writing to the applicable control register after exiting the hibernate state. This may
result in a short interruption to the Current Sink output.
ADDRESS
BIT
9:8
15
14
13
12
CSn_FLASH_M
ODE
CSn_TRIGSRC
CSn_DRIVE
CSn_FLASH_R
ATE
CSn_FLASH_D
UR [1:0]
LABEL
DEFAULT
00
0
0
0
0
Determines the function of the current
sink
0 = LED mode
1 = Flash mode
Selects the trigger in Flash mode.
0 = Flash triggered by CSn_DRIVE bit
1 = Flash triggered from GPIO pin
This bit has no effect when
CSn_FLASH_MODE=0
Enables the current sink ISINKn
LED mode-
0 = disable LED
1 = enabled LED
FLASH mode-
Register bit used to trigger the flash, if
CS1_TRIGSRC is set to 0. Flash is
started when the bit goes high, it is then
reset at the end of the flash duration.
Duration is determined by
CS1_FLASH_DUR. This bit has no effect
if CS1_TRIGSRC is set to 1.
Determines the Flash rate
0 = Normal Operation. Once per trigger
(Either register bit or GPIO)
1 = Flash will be internally triggered
every 4 second
Sets duration of flash
00 = 32ms
01 = 64ms
10 = 96ms
11 = 1024ms
configured as FLASH
DESCRIPTION
PD, March 2010, Rev 4.2
WM8350
151

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