KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet - Page 81

• Manufacturer Part Number: KSZ8893FQL-FX
• Description: 2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8893FQL-FX

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 1000Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3273

Micrel, Inc.
Register 68 (0x44): Loop Back Setup1
October 2007
Bit
Bit
2
1
0
7
6
5
4
3
2
1
0
Name
Enhanced
ML_EN
P1 TX_DIS
PHY reset
Name
T7
T6
T5
T4
T3
T2
T1
T0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
1 = Defined as follows:
In Terminal side MC mode, if a link down is detected on the
fiber or the Center side UTP, the Terminal side will disable the
TX on its UTP and turn off the LEDs to its UTP.
In Center side MC mode, this bit has no meaning.
0 = Normal operation
1 = Disable (tri-state) transmit to Fiber PHY
(port 1)
0 = Normal operation
1 = Reset the PHY of both PHY ports to their default states.
This bit is self-cleared after a ‘1’ is written to it.
0 = Normal operation
Note: MC (maintenance) sub-layer registers are not reset by
this bit.
Description
Center and Terminal sides
0000_0000 : Clear valid transmit and valid receive counters
in registers 4Dh and 4Eh. Also for center side, clear loop back
counters in registers 46h, 47h and 48h.
Center side only
0000_0001 : Send 1 MC loop back packet
0000_0010 : Send 2 MC loop back packets
0000_0111 : Send 7 MC loop back packets (default)
0110_0100 : Send 100 MC loop back
other values (0x65h to 0xFFh) : N/A
:
:
81
packets
M9999-101607-1.3
ML_EN pin
value during
reset
(Powered on
value in Center
side MC mode.
After reg.
0x40h is
programmed,
this bit will be
cleared.)
--------------------
(Default value
for non Center
side MC mode)
KSZ8893FQL
Default
Default
0
1
0
0
0
0
0
0
1
1
1