KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet
KSZ8893FQL-FX
Specifications of KSZ8893FQL-FX
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KSZ8893FQL-FX Summary of contents
Page 1
... General Description The KSZ8893FQL, a highly integrated single-chip 3 port Fast Ethernet switch is designed for applications with fiber support such as media converter. It provides two 10/100 transceivers with patented mixed-signal low- power technology, three media access control (MAC) units, a high-speed non-blocking switch fabric, a Layer-2 ...
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... Low Power Dissipation • Full-chip hardware power-down (register configuration not saved) • Per port based software power-save on PHY (idle link detection, register configuration preserved) • Voltages: – Core 1.2V – I/O and Transceiver 3.3V Available in 128-Pin PQFP, Lead-free package 2 KSZ8893FQL M9999-101607-1.3 ...
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... FTTx Managed/Unmanaged Media Converters • Fiber Broadband Gateways Ordering Information Part Number Temp. Range KSZ8893FQL 0°C to 70°C KSZ8893FQL-FX 0°C to 70°C October 2007 Package Lead Finish Description Port 1 supports 10Base-FL and 100Base-SX with LED 128-Pin PQFP ...
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... Data sheet created. 1.1 02/08/07 Modify Table 10. RMII Signal Connections Add TLA-6T718 to Table 37. Qualified Single Port Magnetics Remove KSZ8893FQLI from the datasheet 1.2 06/19/07 Update Ordering Information Add Thermal Resistance (θ 1.3 10/16/07 Recommend connecting a 100ohm resistor between VDDC and 3.3V power rail. ...
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... MAC Operation ........................................................................................................................................................... 37 Inter Packet Gap (IPG)......................................................................................................................................... 37 Back-Off Algorithm ............................................................................................................................................... 37 Late Collision........................................................................................................................................................ 37 Illegal Frames....................................................................................................................................................... 37 Full Duplex Flow Control ...................................................................................................................................... 37 Half-Duplex Backpressure ................................................................................................................................... 37 Broadcast Storm Protection ................................................................................................................................. 38 MII Interface Operation ............................................................................................................................................... 38 RMII Interface Operation ............................................................................................................................................ 39 SNI (7-Wire) Operation ............................................................................................................................................... 40 MII Management (MIIM) Interface .............................................................................................................................. 41 Serial Management Interface (SMI)............................................................................................................................ 41 October 2007 5 KSZ8893FQL M9999-101607-1.3 ...
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... Register 6 (0x06): Global Control 4...................................................................................................................... 63 Register 7 (0x07): Global Control 5...................................................................................................................... 64 Register 8 (0x08): Global Control 6...................................................................................................................... 64 Register 9 (0x09): Global Control 7...................................................................................................................... 64 Register 10 (0x0A): Global Control 8 ................................................................................................................... 65 Register 11 (0x0B): Global Control 9 ................................................................................................................... 65 Register 12 (0x0C): Global Control 10 ................................................................................................................. 65 Register 13 (0x0D): Global Control 11 ................................................................................................................. 66 October 2007 6 KSZ8893FQL M9999-101607-1.3 ...
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... Register 62 (0x3E): Reserved, not applied to port 3............................................................................................ 77 Register 31 (0x1F): Port 1 Status 1...................................................................................................................... 78 Register 47 (0x2F): Port 2 Status 1...................................................................................................................... 78 Register 63 (0x3F): Port 3 Status 1...................................................................................................................... 78 TS-1000 Media Converter Registers .......................................................................................................................... 79 Register 64 (0x40): PHY Address ........................................................................................................................ 79 Register 65 (0x41): Center Side Status ............................................................................................................... 79 Register 66 (0x42): Center Side Command......................................................................................................... 80 October 2007 7 KSZ8893FQL M9999-101607-1.3 ...
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... Register 114 (0x72): MAC Address Register 2.................................................................................................... 93 Register 115 (0x73): MAC Address Register 3.................................................................................................... 93 Register 116 (0x74): MAC Address Register 4.................................................................................................... 93 Register 117 (0x75): MAC Address Register 5.................................................................................................... 93 User Defined Registers............................................................................................................................................... 93 Register 118 (0x76): User Defined Register 1 ..................................................................................................... 93 October 2007 8 KSZ8893FQL M9999-101607-1.3 ...
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... Additional MIB Counter Information ................................................................................................................... 103 (1) Absolute Maximum Ratings ...................................................................................................................................... 104 (2) Operating Ratings ...................................................................................................................................................... 104 (4) Electrical Characteristics .......................................................................................................................................... 104 Timing Diagrams ........................................................................................................................................................... 106 EEPROM Timing ...................................................................................................................................................... 106 SNI Timing ................................................................................................................................................................ 107 MII Timing ................................................................................................................................................................. 108 RMII Timing............................................................................................................................................................... 109 SPI Input Timing ....................................................................................................................................................... 110 SPI Output Timing .................................................................................................................................................... 111 Auto-Negotiation Timing ........................................................................................................................................... 112 October 2007 9 KSZ8893FQL M9999-101607-1.3 ...
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... Micrel, Inc. List of Figures Figure 1. TS-1000 OAM Frame Format ........................................................................................................................... 23 Figure 2. Typical TS-1000 Media Converter Application ................................................................................................. 24 Figure 3. KSZ8893FQL MC Loop Back Paths ................................................................................................................. 25 Figure 4. Typical Straight Cable Connection ................................................................................................................... 31 Figure 5. Typical Crossover Cable Connection ............................................................................................................... 31 Figure 6. Auto-Negotiation and Parallel Operation. ......................................................................................................... 32 Figure 7. Destination Address Lookup Flow Chart, Stage 1 ............................................................................................ 35 Figure 8 ...
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... Table 17. STPID Egress Rules (Switch Port 3 to Processor) .......................................................................................... 44 Table 18. FID+DA Lookup in VLAN Mode ....................................................................................................................... 45 Table 19. FID+SA Lookup in VLAN Mode ....................................................................................................................... 45 Table 20. KSZ8893FQL SPI Connections ....................................................................................................................... 49 Table 21. Format of Static MAC Table (8 Entries) ........................................................................................................... 97 Table 22. Format of Static VLAN Table (16 Entries)........................................................................................................ 99 Table 23. Format of Dynamic MAC Address Table (1K Entries) ................................................................................... 100 Table 24. Format of “ ...
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... UNUSED 119 UNUSED 120 UNUSED 121 UNUSED 122 DGND VDDC 123 UNUSED 124 UNUSED 125 UNUSED 126 TESTEN 127 SCANEN 128 October 2007 128-Pin PQFP (Q) (Top View) 12 KSZ8893FQL 64 AGND 63 VDDAP 62 AGND 61 ISET 60 TEST2 59 TEST1 58 AGND 57 VDDA 56 TXP2 55 TXM2 54 AGND 53 RXP2 52 ...
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... Low (collision) RPT_LINK#/ port): Low (link), High (no link), Toggles (receive activity) Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P1LED3 is pin 25. During reset, P1LED[2:0] are inputs for internal testing. 13 KSZ8893FQL [0,1] — 100Link/Act 10Link/Act Full duplex [1,1] — — — ...
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... Low (error status due to either isolation, partition, jabber error) Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P2LED3 is pin 20. During reset, P2LED[2:0] are inputs for internal testing. Digital ground 3.3V digital KSZ8893FQL [0,1] — 100Link/Act 10Link/Act Full duplex [1,1] — — — ...
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... Ipd 15 P2DPX Ipd 16 P2FFC Ipd October 2007 (1) Pin Function KSZ8893FQL operating modes (defined below): (MCHS, MCCS) Description Normal 3 port switch mode (3 MAC + 2 PHY) MC mode is disabled. Port 1 is either Fiber or UTP. (0, 0) Port 2 is UTP. Port 3 (MII) is enabled. Center MC mode (3 MAC + 2 PHY) MC mode is enabled ...
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... ON the LED. See description in pin 4. Digital ground 1.2V digital V DD Provides V to KSZ8893FQL’s input power pins: V OUT_1V2 and 123), and V (pins 38, 43, and 57 recommended the pin should be DDA connected to 3.3V power rail by a 100ohm resistor for the internal LDO application. ...
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... V DD Analog ground I Factory test pin – float for normal operation I Factory test pin – float for normal operation Set physical transmit output current Pull-down this pin with a 3.01K 1% resistor to ground. Analog ground 1.2V analog V for PLL DD Analog ground 17 KSZ8893FQL M9999-101607-1.3 ...
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... Switch MII receive data bit 1 Strap option: Switch MII (default) = 100Mbps mode PU = 10Mbps mode Switch MII receive data bit 0 Strap option: switch will accept packet size 1536 bytes (inclusive 1522 bytes (tagged), 1518 bytes (untagged) Switch MII collision detect 18 KSZ8893FQL M9999-101607-1.3 ...
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... See description in pins 100 and 101. Note: an external pull-up is needed on this pin when use. I SPI slave mode: chip select (active low) When SPIS_N is high, the KSZ8893FQL is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pins 100 and 101. ...
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... I SPIS_N I [PS1, PS0] = [1, 1] – SMI-mode In this mode, the KSZ8893FQL provides access to all its internal 8-bit registers through its MDC and MDIO pins. Note: When (PS1, PS0) ≠ (1,1), the KSZ8893FQL provides access to its 16-bit MIIM registers through its MDC and MDIO pins. ...
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... Unused pin – externally pull down for normal operation I Unused pin – externally pull down for normal operation Scan Test Enable For normal operation, pull-down this pin to ground. Scan Test Scan Mux Enable For normal operation, pull-down this pin to ground. 21 KSZ8893FQL M9999-101607-1.3 ...
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... Converter (MC) applications, PHY port 1 is the fiber port and supports 100Base-FX, 100Base-SX and 10Base-FL. The KSZ8893FQL has the flexibility to reside in either a managed or unmanaged design managed design, the host processor has complete control of the KSZ8893FQL via the SMI interface, MIIM interface, SPI bus unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time ...
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... MC have to set always “0”) 0: Not Support Auto-Negotiation 1: Support Auto-Negotiation (Center side MC have to set always “0”) 0: one link partner on UTP side 1: multiple link partner on UTP side All bits must be set “0” Create FCS at this sub-layer (C0-M47) Figure 1. TS-1000 OAM Frame Format 23 KSZ8893FQL M9999-101607-1.3 ...
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... Pin Description and I/O Assignment section. (MCHS, MCCS) (0, 0) (0, 1) (1, 0) (1, 1) The following figure shows two KSZ8893FQLs connected in a typical center MC to terminal MC application. October 2007 Description Normal 3 port switch mode (3 MAC + 2 PHY) MC mode is disabled. Port 1 is either Fiber or UTP. ...
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... Micrel, Inc. MC Loop Back Operation TS-1000 MC loop back operation is initiated and enabled by the center MC. The terminal MC provides the loop back path to return the loop back packet back to the center MC. The KSZ8893FQL in terminal MC mode provides three loop back path options: Port 1 OPT • ...
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... Micrel, Inc. Dedicated TS-1000 Registers & Pins The KSZ8893FQL provides 32 dedicated registers to support TS-1000 OAM communication in center MC and terminal MC modes. The TS-1000 MC registers are located (0x40 to 0x5F), and provide the following functions: • PHY address configuration • Center MC and Terminal MC configuration • ...
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... Micrel, Inc. 10Base-FL Operation 10Base-FL operation is supported on port 1 of the KSZ8893FQL. It conforms to clause 15 and 18 of the IEEE802.3 Standard for 10Base-FL fiber operation. Refer to the Standard for details typical application, the KSZ8893FQL provides media conversion from 10Base-FL fiber on port 1 to 10Base-T copper on port 2. Alternatively, port 2 can be substituted with port 3 to directly connect to an external MAC. ...
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... Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KSZ8893FQL generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50MHz oscillator or system clock ...
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... A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KSZ8893FQL detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the KSZ8893FQL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between frames. ...
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... PIN diode module. The minimum sensitivity of the post amplifier is 2.5mV Power Management The KSZ8893FQL features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via port control register, or via MIIM PHY register. In addition, there is a full chip power down mode. When activated, the entire chip is powered down. ...
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... Figure 4. Typical Straight Cable Connection 1 Crossover Cable HUB Figure 5. Typical Crossover Cable Connection 31 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) M9999-101607-1.3 KSZ8893FQL ...
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... If auto-negotiation is not supported or the KSZ8893FQL link partner is forced to bypass auto-negotiation, then the KSZ8893FQL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8893FQL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. ...
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... The ‘11’ case, invalid test, occurs when the KSZ8893FQL is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8893FQL to determine if the detected signal is a reflection of the signal generated or a signal from another source ...
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... Forwarding The KSZ8893FQL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 7 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “ ...
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... Micrel, Inc. Figure 7. Destination Address Lookup Flow Chart, Stage 1 October 2007 35 KSZ8893FQL M9999-101607-1.3 ...
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... These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegally sized packet errors. 2. IEEE802.3x PAUSE frames KSZ8893FQL intercepts these packets and performs full duplex flow control accordingly. 3. "Local" packets Based on destination address (DA) lookup. If the destination port from the look-up table matches the port from which the packet originated, the packet is defined as " ...
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... The KSZ8893FQL will flow control a port that has just received a packet if the destination port resource is busy. The KSZ8893FQL issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802.3x standard ...
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... Note: These bits are not set as defaults, as this is not the IEEE standard. Broadcast Storm Protection The KSZ8893FQL has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8893FQL has the option to include “ ...
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... MAC device. Since the switch filters error frames, these MII error signals are not used by the KSZ8893FQL. So, for PHY mode operation, if the device interfacing with the KSZ8893FQL has an MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8893FQL has an MTXER input pin, it also needs to be tied low. ...
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... Micrel, Inc. The KSZ8893FQL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from RMII PHY devices, the SMTXER input signal of the KSZ8893FQL is connected to the RXER output signal of the RMII PHY device. Collision detection is implemented in accordance with the RMII Specification. ...
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... Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8893FQL. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification. ...
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... Repeater Mode The KSZ8893FQL supports repeater mode in 100Base-TX Half Duplex mode. In repeater mode, all ingress packets are broadcast to the other two ports. MAC address checking and learning are disabled. Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be configured to 100Base-TX Half Duplex mode ...
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... MAC table lookup to determine the forwarding port(s). The KSZ8893FQL uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override any port setting, regardless of port states (disable, blocking, listening, and learning). The table below shows the processor to switch egress rules when dealing with STPID. TX port “ ...
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... A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8893FQL forwards the packet to both port 2 and port 3. The KSZ8893FQL can optionally even forward “bad” received packets to the “sniffer port”. ...
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... Update time stamp Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KSZ8893FQL. These features can be set on a per port basis, and are defined in register 18, 34 and 50 for ports 1, 2 and 3, respectively. ...
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... Tag Insertion is enabled by bit [2] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KSZ8893FQL will not add tags to already tagged packets. ...
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... MAC address to a specific port unicast MAC address is not recorded in the static table also not learned in the dynamic MAC table. The KSZ8893FQL is then configured with the option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register 14 ...
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... C slave mode by setting the KSZ8893FQL strap-in pins PS[1:0] (pins 100 and 101, respectively) to “01”. 2. Power up the board and assert reset to the KSZ8893FQL. After reset, the “Start Switch” bit (register 1 bit [0]) is set to ‘0’. 3. Configure the desired register settings in the KSZ8893FQL, using the I ...
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... The KSZ8893FQL internal address counter increments automatically to the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8893FQL SDA input pin is written to the next register address. SPI multiple write continues until the SPI master device terminates it by de- asserting the SPIS_N signal to the KSZ8893FQL ...
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... The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of SPIC. October 2007 Figure 11. SPI Write Data Cycle Figure 12. SPI Read Data Cycle 50 KSZ8893FQL M9999-101607-1.3 ...
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... Micrel, Inc. October 2007 Figure 13. SPI Multiple Write Figure 14. SPI Multiple Read 51 KSZ8893FQL M9999-101607-1.3 ...
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... Micrel, Inc. Loopback Support The KSZ8893FQL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100Base-TX. Two types of loopback are supported: (Remote) Loopback. Far-end Loopback Far-end loopback is conducted between the KSZ8893FQL’s two PHY ports. The loopback path starts at the “ ...
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... Micrel, Inc. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8893FQL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXPx/TXMx). ...
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... PHY2 Basic Control Register PHY2 Basic Status Register PHY2 Physical Identifier I PHY2 Physical Identifier II PHY2 Auto-Negotiation Advertisement Register PHY2 Auto-Negotiation Link Partner Ability Register PHY2 Not supported PHY2 LinkMD Control/Status PHY2 Not supported PHY2 Special Control/Status 54 KSZ8893FQL 2 C, and SMI interfaces can M9999-101607-1.3 ...
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... Normal operation (transmit on TXP / TXM pins) R Disable auto MDI Enable auto MDI-X R Disable far-end fault detection 0 = Normal operation R Disable transmit 0 = Normal operation R Disable LED 0 = Normal operation 55 KSZ8893FQL Default Reference 0 0 Reg. 29, bit 0 Reg. 45, bit 0 0 Reg. 28, bit 6 Reg. 44, bit 6 1 Reg. 28, bit 7 Reg. 44, bit 7 0 Reg ...
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... Not auto-negotiation capable Link Link is down RO NOT SUPPORTED Not extended register capable R/W Description RO High order PHYID bits R/W Description RO Low order PHYID bits 56 KSZ8893FQL Default Reference 0 1 Always 1 1 Always 1 1 Always 1 1 Always 1 0000 0 0 Reg. 30, bit 6 Reg. 46, bit 6 0 Reg ...
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... NOT SUPPORTED RO RO Link partner pause capability RO RO Link partner 100 full capability RO Link partner 100 half capability RO Link partner 10 full capability RO Link partner 10 half capability RO 57 KSZ8893FQL Default Reference Reg. 28, bit 4 Reg. 44, bit Reg. 28, bit 3 Reg. 44, bit 3 1 Reg. 28, bit 2 Reg ...
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... End: TXP1/TXM1 (port 1) Port 2 (reg. 42, bit 1 = ‘1’) Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 2’s PHY End: TXP2/TXM2 (port Normal Operation R/W Reserved Do not change the default value. 58 KSZ8893FQL Default Reference 0 Reg. 26, bit 4 Reg. 42, bit 4 00 Reg 26, bit[6:5] Reg 42, bit[6:5] 0 Reg. 26, bit 7 Reg ...
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... My Vendor Info (1) My Vendor Info (2) My Vendor Info (3) My Model Info (1) My Model Info (2) My Model Info (3) LNK Partner Status (1) LNK Partner Status (2) LNK Partner Vendor Info (1) LNK Partner Vendor Info (2) LNK Partner Vendor Info (3) LNK Partner Model Info (1) 59 KSZ8893FQL M9999-101607-1.3 ...
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... EEPROM will be checked. The switch will check: (1) Register 0 = 0x88, (2) Register 1 bits [7:4] = 0xA. If this check is OK, the contents in the EEPROM will override chip registers’ default values Chip will not start when external pins (PS1, PS0) = (0,1) or (1,0) or (1,1). 60 KSZ8893FQL Default 0x88 Default 0xA - - ...
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... Length/Type field < 1500). R Enable age function in the chip 0 = Disable age function in the chip R Turn on fast age (800us) R Enable more aggressive back off algorithm in half duplex mode to enhance performance. This is not an IEEE standard. 61 KSZ8893FQL Default 0 100 Default 0 0 ...
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... Each port is pre-allocated 48 buffers for high priority (q3, q2, and q1) packets. This selection is effective only when the multiple queue feature is turned on recommended to enable this bit for multiple queue reserved buffers for high priority packets. Each port is pre-allocated 48 buffers for all priority packets (q3, q2,q1, and q0). 62 KSZ8893FQL Default ...
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... Description R Enable repeater mode 0 = disable repeater mode Note: For repeater mode, all ports need to be set to 100Base-TX and half duplex mode. PHY ports need to have auto-negotiation disabled. R Enable MII interface half-duplex mode Enable MII interface full-duplex mode. 63 KSZ8893FQL Default Default 0 Pin SMRXD2 strap option ...
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... The default is 1%. R/W Description R/W Reserved Do not change the default values. R/W Description R/W Reserved Do not change the default values. 64 KSZ8893FQL Default Pin SMRXD3 strap option. Pull-down(0): Disable flow control Pull- up(1): Enable flow control Note: SMRXD3 has internal pull- down ...
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... IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x1. R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x0. 65 KSZ8893FQL Default 0x35 Default LEDSEL1 (pin 23) value ...
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... Port 1 PHY address is 0x1 00010 : Port 1 PHY address is 0x2 … 11101 : Port 1 PHY address is 0x29 11110 : N/A 11111 : N/A Note: Port 2 PHY address = (Port 1 PHY address Reserved Do not change the default values. 66 KSZ8893FQL Default Default 0 0x0 111 Default 00001 000 ...
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... The switch will not modify packets received without tags Disable tag removal R The port output queue is split into four priority queues Single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority. 67 KSZ8893FQL Default ...
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... Define the port’s egress port VLAN membership. The port can only communicate within the membership. Bit 2 stands for port 3, bit 1 stands for port 2, bit 0 stands for port 1. A ‘1’ includes a port in the membership. A ‘0’ excludes a port from membership. 68 KSZ8893FQL Default ...
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... R Disable switch address learning capability 0 = Enable switch address learning R/W Description R/W Port’s default tag, containing 7-5 : User priority bits 4 : CFI bit 3-0 : VID[11:8] 69 KSZ8893FQL Default Pin value during reset: For port 1, P1FFC pin For port 2, P2FFC pin For port 3, this bit has no meaning ...
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... Ingress and Egress rate limiting calculations IFG bytes are not counted. R/W Count Preamble bytes 1 = Each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations Preamble bytes are not counted. 70 KSZ8893FQL Default 0x01 Default 0x0 M9999-101607-1.3 ...
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... Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). 71 KSZ8893FQL Default 0x0 0x0 M9999-101607-1.3 ...
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... Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). 72 KSZ8893FQL Default 0x0 0x0 M9999-101607-1.3 ...
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... Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). When TX multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 73 KSZ8893FQL Default 0x0 0x0 M9999-101607-1.3 ...
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... Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). When TX multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 74 KSZ8893FQL Default 0x0 0x0 M9999-101607-1.3 ...
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... Port 2 (reg. 42, bit 1 = ‘1’) Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 2’s PHY End: TXP2/TXM2 (port Normal Operation RO Bit[8] of VCT fault count Distance to the fault. It’s approximately 0.4m*vct_fault_count[8:0] R/W Description RO Bits[7:0] of VCT fault count Distance to the fault. It’s approximately 0.4m*Vct_fault_count[8:0] 75 KSZ8893FQL Default Default 0x00 M9999-101607-1.3 ...
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... Advertise 10BT full duplex capability 0 = Suppress 10BT full duplex capability from transmission to link partner R Advertise 10BT half duplex capability 0 = Suppress 10BT half duplex capability from transmission to link partner 76 KSZ8893FQL Default For port 1, P1ANEN pin value during reset. For port 2, P2ANEN pin ...
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... Loopback: PMD/PMA of port 2’s PHY End: TXP1/TXM1 (port Normal operation R/W Description MDI MDI Auto-negotiation completed 0 = Auto-negotiation not completed Link good 0 = Link not good 77 KSZ8893FQL Default Note: Only port 1 supports fiber. This bit is applicable to port 1 only For port 2, P2MDIXDIS pin value during reset ...
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... Receive flow control feature is active 0 = Receive flow control feature is inactive Link speed is 100Mbps 0 = Link speed is 10Mbps Link duplex is full 0 = Link duplex is half Far-end fault status detected Far-end fault status detected 78 KSZ8893FQL Default Default 1 Note: Only ports 1 and 2 are PHY ports. This bit is not applicable to port 3 (MII) ...
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... Normal operation – supporting option b R Disable “Indicate Center MC Condition” frame 0 = Enable “Indicate Center MC condition” frame indicate change of status/value in registers # 0x50h, 0x51h, 0x58h, 0x59h, 0x5Dh, 0x5Eh, 0x5Fh. This bit is self- cleared after a read exclude the above situations 79 KSZ8893FQL Default 000 Default 0 ...
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... Reset MC sub-layer, MACs of both PHY ports and switch fabric to their default states. This bit is self-cleared after a ‘1’ is written to it Normal operation R Enable “Remote Command” access at Center side and Terminal side 0 = Disable “Remote Command” access at Center side and Terminal side 80 KSZ8893FQL Default 001 interface ...
Page 81
... Send 1 MC loop back packet R/W 0000_0010 : Send 2 MC loop back packets R/W : 0000_0111 : Send 7 MC loop back packets (default) : 0110_0100 : Send 100 MC loop back other values (0x65h to 0xFFh) : N/A 81 KSZ8893FQL Default ML_EN pin value during reset 0 1 (Powered on value in Center side MC mode. ...
Page 82
... This counter is cleared when 0x00h is written to reg. 0x44h. R/W Description RO Center side only RO This counter is incremented when loop back packet has timeout 0000_0000 : No timeout occurred RO 0000_0001 : 1 timeout occurred 1111_1111 : 255 timeouts occurred RO This counter is cleared when 0x00h is written to reg. 0x44h. 82 KSZ8893FQL Default Default Default ...
Page 83
... This bit is self-cleared after it is read Normal operation Center side does not receive reply frame from the Terminal side and the TE timer has timeout. This bit is self- cleared after it is read Normal operation Link is down on port Link port 1 83 KSZ8893FQL Default Default ...
Page 84
... If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M39-M32 of the R/W Maintenance frame, instead of register 0x56h. R/W R/W [AMM39:AMM32] = bits[7:0] of the KSZ8893FQL address byte R/W if the Operating Mode in register 0x4Ah bits[1:0] is set to “10” R/W R/W R/W ...
Page 85
... If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M47-M40 of the R/W Maintenance frame, instead of register 0x57h. R/W R/W [AMM47:AMM40] = bits[7:0] of the KSZ8893FQL data byte if R/W the Operating Mode in register 0x4Ah bits[1:0] is set to “10” R/W R/W R/W ...
Page 86
... Reserved Do not change the default values. R/W For Terminal MC mode, this bit must always be “0”. For Center MC mode, this bit indicates the number of physical interface(s) making up the UTP link 0 = One 1 = Greater than one 86 KSZ8893FQL Default 0 1 (Terminal side) 0 (Center side ...
Page 87
... Description R/W Note: If Remote Command feature is used, this register value can not be set to 0x22, 0x26, 0x2A, 0x2E, and 0x66. All other values are valid. R/W Description R/W R/W Description R/W 87 KSZ8893FQL P2ANEN pin value (Terminal MC) -------------------- 0 (Center MC Default 0x00 Default 0x00 ...
Page 88
... This register has the same bits descriptions as register 81 (0x51). R/W Description RO R/W Description RO R/W Description RO R/W Description RO R/W Description RO R/W Description RO 88 KSZ8893FQL Default 0x47 (Center side) -------------------- 0x07 (Terminal side) Default 0x00 Default 0x00 Default 0x00 Default 0x00 Default 0x00 Default 0x00 Default 0x00 ...
Page 89
... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x34. R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x30. 89 KSZ8893FQL Default ...
Page 90
... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x74. R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x70. 90 KSZ8893FQL Default ...
Page 91
... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xB4. R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xB0. 91 KSZ8893FQL Default ...
Page 92
... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xF4. R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xF0. 92 KSZ8893FQL Default ...
Page 93
... User Defined Registers Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KSZ8893FQL and the external processor. Register 118 (0x76): User Defined Register 1 Bit ...
Page 94
... R/W Description R/W Bits [63:56] of indirect data R/W Description R/W Bits [55:48] of indirect data R/W Description R/W Bits [47:40] of indirect data R/W Description R/W Bits [39:32] of indirect data 94 KSZ8893FQL Default 000 Default 0000_0000 Default 0 0000 000 Default 0000_0000 Default 0000_0000 Default ...
Page 95
... R/W Factory testing Dbg[7:0] R/W Description R/W Factory testing (dgt_actl0) R/W Description R/W Factory testing (dgt_actl1) R/W Description R/W Factory testing (dgt_actl2) 95 KSZ8893FQL Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 00000 000 Default 0x3F Default 0x00 Default 0x00 Default 0x00 M9999-101607-1 ...
Page 96
... R/W Description R/W Factory testing (dgt_actl3) R/W Description R Factory testing R/W Description R/W Factory testing (dgt_actl4) R/W Description RO Factory testing QM_Debug bit[7:0] R/W Description RO Reserved RO Factory testing QM_Debug bit[8] 96 KSZ8893FQL Default 0x00 Default 00 00_0000 Default 0x40 Default 0x00 Default 0000_000 0 M9999-101607-1.3 ...
Page 97
... The static DA look up result takes precedence over the dynamic DA look-up result. If there match in both tables, then the result from the static table is used. The entries in the static table will not be aged out by the KSZ8893FQL. The static table is accessed by an external processor via the SMI, SPI or I performs all addition, modification and deletion of static MAC table entries ...
Page 98
... Write to reg. 131 (0x83), static table bits [7:0] Write to reg. 121 (0x79) with 0x00 Write to reg. 122 (0x7A) with 0x07 October 2007 nd Entry) // Read static table selected // Trigger the read operation th Entry) // Write static table selected // Trigger the write operation 98 KSZ8893FQL M9999-101607-1.3 ...
Page 99
... Micrel, Inc. VLAN Table The KSZ8893FQL uses the VLAN table to perform look-ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (filter ID), VID (VLAN ID), and VLAN membership as described in the following table. ...
Page 100
... Micrel, Inc. Dynamic MAC Address Table The KSZ8893FQL maintains the dynamic MAC address table. Read access is allowed only. Bit Name 71 Data Not Ready 70-67 Reserved 66 MAC Empty 65- Valid Entries 55-54 Time Stamp 53-52 Source Port 51-48 FID 47-0 MAC Address Table 23. Format of Dynamic MAC Address Table (1K Entries) ...
Page 101
... Micrel, Inc. MIB (Management Information Base) Counters The KSZ8893FQL provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.” ...
Page 102
... Description N/A Reserved RO Counter Value Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources 102 KSZ8893FQL Default N/A 0 M9999-101607-1.3 ...
Page 103
... If bit restart (reread) from this register counter bits [29:24] // Read MIB counter selected // Trigger the read operation // If bit there was a counter overflow valid bit [30 bit restart (reread) from this register counter bits [29:24] // Read MIB counter selected // Trigger the read operation 103 KSZ8893FQL M9999-101607-1.3 ...
Page 104
... DDA DDAP DDC , ).............. +3.135V to +3.465V DDATX DDARX DDIO ) ....................... 0°C to +70°C A ).................. 125°C J (3) ) ............................... 32°C/W JA (3) ) ............................... 10°C/W JC Min Typ 120 90 2.0 –10 2.4 0. 0.5 0.7 400 2.4 1.8 KSZ8893FQL Max Units 0 µ µA 1. 0.5 ns ±0. 1 3.5 ns M9999-101607-1.3 ...
Page 105
... A 5. Current consumption is for the single 3.3V supply KSZ8893FQL device only, and includes the 1.2V supply voltages (V provided by the KSZ8893FQL via power output pin 22. Each PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T. October 2007 ...
Page 106
... Timing Parameter t cyc1 ov1 October 2007 Figure 17. EEPROM Interface Input Timing Diagram Figure 18. EEPROM Interface Output Timing Diagram Description Min Clock cycle Setup time 20 Hold time 20 Output valid 4096 Table 28. EEPROM Timing Parameters 106 Typ Max Unit 16384 4112 4128 ns M9999-101607-1.3 KSZ8893FQL ...
Page 107
... Timing Parameter t cyc2 ov2 October 2007 Figure 19. SNI Timing – Data Received from SNI Figure 20. SNI Timing – Data Input-to-SNI Description Min Clock cycle Setup time 10 Hold time 0 Output valid 0 Table 29. SNI Timing Parameters 107 KSZ8893FQL Typ Max Unit 100 M9999-101607-1.3 ...
Page 108
... October 2007 Figure 21. MII Timing – Data Received from MII Figure 22. MII Timing – Data Input-to-MII Description Min Clock cycle (100Base-TX) Clock cycle (10Base-T) Setup time 10 Hold time 10 Output valid 0 Table 30. MII Timing Parameters 108 KSZ8893FQL Typ Max Unit 40 ns 400 M9999-101607-1.3 ...
Page 109
... RMII Timing Timing Parameter t cyc October 2007 Figure 23. RMII Timing – Data Received from RMII Figure 24. RMII Timing – Data Input-to-RMII Description Min Clock cycle Setup time 4 Hold time 2 Output delay 2.8 Table 31. RMII Timing Parameters 109 KSZ8893FQL Typ Max Unit M9999-101607-1.3 ...
Page 110
... SPIS_N active old time SPIS_N inactive setup time SPIS_N deselect time Data input setup time Data input hold time Clock rise time Clock fall time Data input rise time Data input fall time Table 32. SPI Input Timing Parameters 110 KSZ8893FQL Min Max Unit 5 MHz ...
Page 111
... October 2007 Figure 26. SPI Output Timing Description Min Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time 90 Clock low time 90 SPIQ rise time SPIQ fall time SPIQ disable time Table 33. SPI Output Timing Parameters 111 KSZ8893FQL Max Unit 5 MHz ...
Page 112
... FLP burst to FLP burst FLP burst width Clock/Data Pulse width Clock pulse to Data pulse Clock pulse to Clock pulse Number of Clock/Data pulse per burst Table 34. Auto-Negotiation Timing Parameters 112 Min Typ Max 100 55.5 64 69.5 111 128 139 17 33 KSZ8893FQL Unit µs µs M9999-101607-1.3 ...
Page 113
... Micrel, Inc. Reset Timing The KSZ8893FQL reset timing requirement is summarized in the following figure and table. Timing Parameter After the de-assertion of reset recommended waiting a minimum of 100 us before starting programming on the 2 managed interface (I C slave, SPI slave, SMI, MIIM). October 2007 Figure 28. Reset Timing ...
Page 114
... Micrel, Inc. Reset Circuit The reset circuit in Figure 29 is recommended for powering up the KSZ8893FQL if reset is triggered only by the power supply. The reset circuit in Figure 30 is recommended for applications where reset is driven by another device (e.g., CPU, FPGA, etc),. At power-on-reset and D1 provide the necessary ramp rise time to reset the KSZ8893FQL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up ...
Page 115
... Table 37. Qualified Single Port Magnetics Value 25 ± Table 38. Typical Reference Crystal Characteristics 115 Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Units MHz ppm pF Ω M9999-101607-1.3 KSZ8893FQL ...
Page 116
... Micrel, Inc. Package Information October 2007 128-Pin PQFP (P) 116 KSZ8893FQL M9999-101607-1.3 ...
Page 117
... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. October 2007 © 2006 Micrel, Incorporated. 117 KSZ8893FQL M9999-101607-1.3 ...