KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet - Page 61

• Manufacturer Part Number: KSZ8893FQL-FX
• Description: 2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8893FQL-FX

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 1000Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3273

Micrel, Inc.
Register 2 (0x02): Global Control 0
Register 3 (0x03): Global Control 1
October 2007
6-4
Bit
Bit
7
3
2
1
0
7
6
5
4
3
2
1
0
Name
New Back-off
Enable
Reserved
Pass Flow Control
Packet
Reserved
Reserved
Link Change Age
Name
Pass All Frames
Reserved
IEEE 802.3x Transmit
Direction Flow Control
Enable
IEEE 802.3x Receive
Direction Flow Control
Enable
Frame Length Field
Check
Aging Enable
Fast Age Enable
Aggressive Back-off
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
New back-off algorithm designed for UNH
1 = Enable
0 = Disable
Reserved
Do not change the default value.
1 = Switch will not filter 802.1x “flow control” packets
0 = Switch will filter 802.1x “flow control” packets
Reserved
Do not change the default value.
Reserved
Do not change the default value.
Link change from “link” to “no link” will cause fast aging (<800µs)
to age address table faster. After an age cycle is complete, the
age logic will return to normal aging (about 200 sec).
1 = Enable
0 = Disable
Note: If any port is unplugged, all addresses will be automatically
aged out.
1 = Will enable receive direction flow control feature.
Description
1 = Switch all packets including bad ones. Used solely for
debugging purposes. Works in conjunction with sniffer mode
only.
Reserved
Do not change the default value.
1 = Will enable transmit direction flow control feature.
0 = Will not enable transmit direction flow control feature. Switch
will not generate any flow control (PAUSE) frame.
0 = Will not enable receive direction flow control feature. Switch
will not react to any flow control (PAUSE) frame it receives.
1 = Will check frame length field in the IEEE packets. If the actual
length does not match, the packet will be dropped (for
Length/Type field < 1500).
1 = Enable age function in the chip
0 = Disable age function in the chip
1 = Turn on fast age (800us)
1 = Enable more aggressive back off algorithm in half duplex
mode to enhance performance. This is not an IEEE standard.
61
M9999-101607-1.3
Invert of
P2LED3 (pin
20) value
during reset
Note: P2LED3
has internal
pull-down.
KSZ8893FQL
Default
Default
100
0
0
1
1
0
0
0
0
0
1
0
0