KSZ8851-16MLL TR Micrel Inc, KSZ8851-16MLL TR Datasheet - Page 6

• Manufacturer Part Number: KSZ8851-16MLL TR
• Description: Single Ethernet Port + Generic (16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLL TR

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

Micrel, Inc.
KSZ8851-16MLL/MLLI
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3........................................................... 46
0x5C – 0x5F: Reserved ........................................................................................................................... 46
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 ................................................................... 46
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 ................................................................... 47
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0............................................................ 47
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1............................................................ 47
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2............................................................ 47
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3........................................................... 47
0x6C – 0x6F: Reserved ........................................................................................................................... 47
Transmit Control Register (0x70 – 0x71): TXCR ...................................................................................... 47
Transmit Status Register (0x72 – 0x73): TXSR........................................................................................ 48
Receive Control Register 1 (0x74 – 0x75): RXCR1.................................................................................. 48
Receive Control Register 2 (0x76 – 0x77): RXCR2.................................................................................. 50
TXQ Memory Information Register (0x78 – 0x79): TXMIR ....................................................................... 50
0x7A – 0x7B: Reserved ........................................................................................................................... 50
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR........................................................... 50
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR ................................................. 51
TXQ Command Register (0x80 – 0x81): TXQCR ..................................................................................... 52
RXQ Command Register (0x82 – 0x83): RXQCR .................................................................................... 52
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR ....................................................................... 53
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR....................................................................... 53
0x88 – 0x8B: Reserved............................................................................................................................ 54
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ............................................................ 54
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR........................................................ 54
Interrupt Enable Register (0x90 – 0x91): IER........................................................................................... 54
Interrupt Status Register (0x92 – 0x93): ISR............................................................................................ 55
0x94 – 0x9B: Reserved............................................................................................................................ 56
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR............................................................ 56
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR............................................................... 57
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0............................................................... 57
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1............................................................... 57
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2............................................................... 57
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3............................................................... 57
0xA8 – 0xAF: Reserved ........................................................................................................................... 58
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR ............................................................... 58
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR.............................................................. 58
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR........................................................ 58
0xB6 – 0xBF: Reserved ........................................................................................................................... 58
Chip ID and Enable Register (0xC0 – 0xC1): CIDER ............................................................................... 58
0xC2 – 0xC5: Reserved ........................................................................................................................... 58
Chip Global Control Register (0xC6 – 0xC7): CGCR ............................................................................... 58
Indirect Access Control Register (0xC8 – 0xC9): IACR ............................................................................ 59
0xCA – 0xCF: Reserved .......................................................................................................................... 59
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR ...................................................................... 59
Indirect Access Data High Register (0xD2 – 0xD3): IADHR ..................................................................... 59
Power Management Event Control Register (0xD4 – 0xD5): PMECR ...................................................... 59
Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR .............................................................. 61
PHY Reset Register (0xD8 – 0xD9): PHYRR........................................................................................... 61
August 2009
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M9999-083109-2.0