KSZ8851-16MLL TR Micrel Inc, KSZ8851-16MLL TR Datasheet - Page 42

• Manufacturer Part Number: KSZ8851-16MLL TR
• Description: Single Ethernet Port + Generic (16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLL TR

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

EEPROM Control Register (0x22 – 0x23): EEPCR
To support an external EEPROM, pulled-up the EED_IO pin to High; otherwise, it is pulled-down to Low. If an external
EEPROM is not used, the software programs the host MAC address. If an EEPROM is used in the design, the chip host
MAC address is loaded from the EEPROM immediately after reset. The KSZ8851-16MLL allows the software to access
(read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the
EEPROM Software Access bit is set.
Memory BIST Info Register (0x24 – 0x25): MBIR
This register indicates the build-in self test result for both TX and RX memories after power-up/reset.
Global Reset Register (0x26 – 0x27): GRR
This register controls the global and QMU reset functions with information programmed by the CPU.
August 2009
Micrel, Inc.
Bit
15-6
5
4
3
2-0
Bit
15-13
12
11
10-8
7-5
4
3
2-0
Bit
15-2
1
-
0
0
-
-
-
-
-
-
-
-
0
Default Value
0x0
Default Value
0x0
Default Value
0x0000
R/W
RO
WO
RW
RO
RW
R/W
RO
RO
RO
RO
RO
RO
RO
RO
R/W
RO
RW
Description
Reserved.
EESRWA EEPROM Software Read or Write Access
0: software read enable to access EEPROM when software access enabled (bit4=1)
1: software write enable to access EEPROM when software access enabled (bit4=1).
EESA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable software to access EEPROM.
EESB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EED_IO pin.
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EED_IO pin.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin.
Description
Reserved.
TXMBF TX Memory BIST Test Finish
When set, it indicates the Memory Built In Self Test completion for the TX Memory.
TXMBFA TX Memory BIST Test Fail
When set, it indicates the TX Memory Built In Self Test has failed.
TXMBFC TX Memory BIST Test Fail Count
To indicate the TX Memory Built In Self Test failed count
Reserved.
RXMBF RX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the RX Memory.
RXMBFA RX Memory Bist Fail
When set, it indicates the RX Memory Built In Self Test has failed.
RXMBFC RX Memory BIST Test Fail Count
To indicate the RX Memory Built In Self Test failed count.
Description
Reserved.
QMU Module Soft Reset
1: Software reset is active to clear both TXQ and RXQ memories.
0: Software reset is inactive.
QMU software reset will flush out all TX/RX packet data inside the TXQ and RXQ
memories and reset all QMU registers to default value.
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KSZ8851-16MLL/MLLI
M9999-083109-2.0