KSZ8842-PMBL Micrel Inc, KSZ8842-PMBL Datasheet - Page 48

• Manufacturer Part Number: KSZ8842-PMBL
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1636 - BOARD EVALUATION KSZ8842-PMQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3089

Micrel, Inc.
Interrupt Status Register (INTST Offset 0x002C)
This register contains the status bits for the CPU. When the corresponding bit is set, the CPU is interrupted. The driver
usually reads this register during interrupt service routine or polling. The register bits are not cleared when read. Each
field can be masked.
The following table shows the register bit fields.
October 2007
24 – 0
24 – 0
Bit
Bit
25
31
30
29
28
27
26
25
Default
Default
0
–
0
0
0
0
0
0
0
–
R/W
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
Description
DMRPSIE DMA MAC Receive Process Stopped Interrupt Enable
When this bit is set, the DMA MAC Receive Process Stopped Interrupt is
enabled.
When this bit is reset, the DMA MAC Receive Process Stopped Interrupt
is disabled.
Reserved
Description
DMLCS DMA MAC Link Changed Status
When this bit is set, it indicates that the DMA MAC link status has
changed from link up to link down or from link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
DMTS DMA MAC Transmit Status
When this bit is set, it indicates that the DMA MAC has transmitted at
least a frame on the DMA port and the MAC is ready for new frames from
the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
DMRS DMA MAC Receive Status
When this bit is set, it indicates that the DMA MAC has received a frame
from the DMA port and it is ready for the host to process
This edge-triggered interrupt status is cleared by writing 1 to this bit.
DMTBUS DMA MAC Transmit Buffer Unavailable Status
When this bit is set, it indicates that the next descriptor on the transmit list
is owned by the host and cannot be acquired by the KSZ8842-
PMQL/PMBL. The transmission process is suspended. To resume
processing transmit descriptors, the host should change the ownership bit
of the descriptor and then issue a transmit start command.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
DMRBUS DMA MAC Receive Buffer Unavailable Status
When this bit is set, it indicates that the descriptor list is owned by the host
and cannot be acquired by the KSZ8842-PMQL/PMBL. The receiving
process is suspended. To resume processing receive descriptors, the
host should change the ownership of the descriptor and may issue a
receive start command. If no receive start command is issued, the
receiving process resumes when the next recognized incoming frame is
received. After the first assertion, this bit is not asserted for any
subsequent not owned receive descriptors fetches. This bit is asserted
only when the previous receive descriptor was owned by the KSZ8842-
PMQL/PMBL.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
DMTPSS DMA MAC Transmit Process Stopped Status
Asserted when the DMA MAC transmit process enters the stopped state.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
DMRPSS DMA MAC Receive Process Stopped Status
Asserted when the DMA MAC receive process enters the stopped state.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
48
KSZ8842-PMQL/PMBL
M9999-100207-1.5