KSZ8842-PMBL Micrel Inc, KSZ8842-PMBL Datasheet - Page 14

• Manufacturer Part Number: KSZ8842-PMBL
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1636 - BOARD EVALUATION KSZ8842-PMQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3089

Micrel, Inc.
October 2007
Pin
Number
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
DEVSELN
PERRN
SERRN
Pin
Name
TRDYN
STOPN
CBE3N
CBE2N
CBE1N
CBE0N
VDDIO
PAD31
VDDIO
PAD30
PAD29
PAD28
IDSEL
REQN
GNTN
DGND
DGND
VDDC
NC
NC
NC
NC
Type
Gnd
Gnd
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
O
P
O
P
P
I
I
I
I
I
PCI Target Ready
As a bus target, this signal is asserted low to indicate valid data phases on PAD [31:0]
during read data phases, indicating it is ready to accept data during write data phases.
As a master, it will monitor this TRDYN signal that indicates the target is ready for data
during read/write operation.
PCI Stop
This signal is asserted low by the target device to stop the current transaction.
PCI Initialization Device Select
This signal is used to select the KSZ8842-PMQL during configuration read and write
transactions.
PCI Device Select
This signal is asserted low when it is selected as a target during a bus transaction. As a
bus master, the KSZ8842-PMQL samples this signal to insure that the destination
address for the data transfer is recognized by a PCI target.
PCI Bus Request
The KSZ8842-PMQL will assert this signal low to request PCI bus master operation.
PCI Bus Grant
This signal is asserted low to indicate to the KSZ8842-PMQL that it has been granted
the PCI bus master operation.
PCI Parity Error
The KSZ8842-PMQL as a master or target will assert this signal low to indicate a parity
error on any incoming data. As a bus master, it will monitor this signal on all write
operations.
Digital I/O ground
3.3V digital I/O V
PCI System Error
This system error signal is asserted low by the KSZ8842-PMQL.This signal is used to
report address parity errors.
No connect
No connect
No connect
No connect
Command and Byte Enable
These signals are multiplexed on the same PCI pins. During the address phase, these
lines define the bus command. During the data phase, these lines are used as Byte
Enables. The Byte enables are valid for the entire data phase and determine which byte
lanes carry meaningful data.
PCI Address / Data 31
Address and data are multiplexed on the all of the PAD pins. The PAD pins carry the
physical address during the first clock cycle of a transaction, and carry data during the
subsequent clock cycles.
Digital core ground
1.2V digital core V
3.3V digital I/O V
PCI Address / Data 30
PCI Address / Data 29
PCI Address / Data 28
Pin Function
DD
DD
DD
14
KSZ8842-PMQL/PMBL
M9999-100207-1.5