KSZ8842-PMBL Micrel Inc, KSZ8842-PMBL Datasheet - Page 46

• Manufacturer Part Number: KSZ8842-PMBL
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1636 - BOARD EVALUATION KSZ8842-PMQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3089

Micrel, Inc.
MAC DMA Receive Start Command Register (MDRSC Offset 0x000C)
This register is written by the CPU when there are frame data in receive buffer to be processed.
The following table shows the register bit fields.
Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)
This register is used for the Transmit Descriptor List Base Address. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8842-PMQL/PMBL behavior is unpredictable when
the lists are not word-aligned.
The following table shows the register bit fields.
Receive Descriptor List Base Address Register (RDLB Offset 0x0014)
This register is used for the Receive descriptor list base address. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8842-PMQL/PMBL behavior is unpredictable when
the lists are not word-aligned
The following table shows the register bit fields.
Reserved (Offset 0x0018)
The following table shows the register bit fields.
Reserved (Offset 0x001C)
The following table shows the register bit fields.
MAC Multicast Table 0 Register (MTR0 Offset 0x0020)
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of
the CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within
the register.
October 2007
31 – 0
31 – 0
31 – 0
31 – 0
31 – 0
Bit
Bit
Bit
Bit
Bit
0x00000000
Default \
Default
Default
Default
Default
0x0
0x0
0x0
0x0
.
Read/
Write
R/W
R/W
R/W
R/W
WO
RW
RW
RO
RO
Description
WRSC Receive Start Command
When written with any value, the Receive DMA checks for descriptors to
be acquired. If no descriptor is available, the receive process returns to
suspended state and waits for the next receive restart command. If
descriptiors are available, the receive process resumes.
This bit is self-clearing.
Description
WSTL Start of Transmit List
Note: Write can only occur when the transmit process stopped.
Description
WSRL Start of Receive List
Note: Write can only occur when the transmit process stopped.
Description
Reserved
Description
Reserved
46
KSZ8842-PMQL/PMBL
M9999-100207-1.5