EVAL-AD5560EBUZ Analog Devices Inc, EVAL-AD5560EBUZ Datasheet - Page 35

• Manufacturer Part Number: EVAL-AD5560EBUZ
• Description: Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5560EBUZ

• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Utilized Ic / Part: AD5560
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POLES AND ZEROS IN A TYPICAL SYSTEM
Typical closed loop systems have one dominant pole in the
feedback path, providing −20 dB/decade gain roll off and 90°
of phase shift so that the gain decreases to 0 dB where there
is a conservative 90° of phase margin.
The AD5560 has compensation options to help cope with the
various load conditions that a DPS is presented with.
MINIMIZING THE NUMBER OF EXTERNAL
COMPENSATION COMPONENTS
Note that, depending on the range of load conditions, not all
external capacitors are required.
C
There are five external C
in the autocompensation mode to choose a suitable capacitor,
depending on the load being driven. To reduce component
count, it is possible to connect just one capacitor, for instance,
C
smallest three external capacitors are selected, the same physical
capacitor is used because it is connected to all three pins. A
disadvantage here is that the larger C
bigger than optimal and may increase settling time of the
whole circuit (particularly the measure current).
C
To make the AD5560 stable with any unknown capacitor
from 0 pF to 160 μF, all four C
However, if the range of load is from 0 pF to 20 μF, then
C
2.2 μF, then C
in autocompensation mode.
Note that safe mode, which makes the device stable in any
load from 0 pF to 160 μF, simply switches in all of the four
C
capacitors are present; otherwise, the maximum capacitor for
stability is reduced to 20 μF, 2.2 μF, or 220 nF, depending on
how many capacitors are missing.
EXTRA POLES AND ZEROS IN THE AD5560
The Effect of C
C
nected in addition to C
In the ±500 mA range looking into a small load capacitor, with
only C
~90° of phase margin and a unity gain bandwidth (UGB) of
~400 kHz.
The Effect of C
The output of the AD5560 passes through a sense resistor to
the DUT. Coupled with the load capacitor, this sense resistor
can act as a low-pass filter that adds phase shift and decreases
phase margin (particularly in the low current ranges where the
sense resistors are large).
Fx
Cx
F2
C3
Cx
C0
Pins
to the C
Pins
capacitors. Stability into 160 μF is assured only if all four
can be omitted. Similarly, if the load range is from 0 pF to
is switched on at all times. C
C0
connected, the ac gain vs. phase response results in
F2
, C
C2
F1
Cx
Fx
and C
, and C
C3
C0
F0
can be omitted. Only C
Fx
to slow down the force amplifier loop.
pins. Therefore, when any of the
pins. All five pins are used
Cx
C3
capacitors are required.
, C
C2
F2
, and C
capacitor should be
C1
C0
can be con-
is required
Rev. C | Page 35 of 60
Placing a capacitor in parallel with this sense resistor provides
an ac feedforward path to the DUT. Therefore, at high frequen-
cies, the DUT is driven through the C
through the sense resistor.
Note that each C
3 Ω. This is very small compared to the sense resistors of the
low current ranges but not so for the highest current ranges.
Therefore, the C
ranges but are of lesser benefit in higher current ranges.
As shown in the force amplifier diagram (see Figure 55), there
is a pole at 1/( R
Therefore, the output impedance of each C
1 Ω, limits the improvement available by using the C
tors. For a large load capacitance, there is still a pole at −1/[1 Ω
× C
also a cable resistance to the DUT, or if C
this should be added to the 1 Ω to calculate the pole frequency.
If C
dominate the settling time and slow down the settling of the
whole circuit. Also, it directly affects the time taken to measure
a current (R
The Effect of R
When the load capacitance is known, R
ize the response of the AD5560. Because the C
some output impedance of about 1 Ω, there is likely to be some
additional resistance to the DUT. There can still be an output
pole associated with this resistance and the load capacitance,
C
the sense resistor, the C
ESR, and the cable to DUT). This is particularly significant for
larger load capacitances in any current range. By programming
a zero into the loop response by setting R
it is possible to cancel this pole. Above the frequency 1/[C
R
rather than capacitive, and the 90° phase shift and 20 dB/decade
contributed by C
load pole with the R
exist. Adding a zero to cancel a pole that does not exist causes
an oscillation (perhaps the expected load capacitor is not
present). Also, it is recommended to avoid creating a zero
frequency lower than the pole frequency; instead, allow the zero
frequency to be 2× or 3× higher than the calculated pole
frequency.
The Effect of R
R
capacitor with significant ESR is present. Above the frequency,
1/[C
DUT capacitor, R
load capacitor, C
the user has cancelled the load pole with the R
absence of C
the presence of ESR R
Z
P
R
], the series resistance and capacitance begin to look resistive
, 1/[R
can be used to ensure circuit stability when a poor load
R
Fx
] above which the phase improvement is lost. If there is
R
is chosen to be bigger than the load capacitance, it can
× R
0
× C
C
], the DUT begins to look resistive. The ESR of the
SENSE
R
R
] (where R
under these circumstances can cause oscillations,
Fx
Z
P
SENSE
Fx
× C
C0
R
capacitors are most effective in the low current
C
, is counted on to stabilize the system when
, contributes a zero at this frequency. The
output has an output impedance of about
no longer apply. Note that, to cancel the
Z
Fx
× [C
zero, the load pole must be known to
).
C
while nonzero R
Fx
0
Fx
= the series/parallel combination of
output impedance, the C
+ C
R
]) and a zero at 1/[ R
Fx
Z
capacitor rather than
Z
can be used to optim-
Z
Fx
is used can cause
(in series with C
Fx
has significant ESR,
output, at around
Z
Fx
zero. Just as the
buffers have
Fx
AD5560
SENSE
capacitor
Fx
capaci-
× C
C0
C0
×
),
Fx
].