EVAL-AD1939AZ Analog Devices Inc, EVAL-AD1939AZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD1939AZ
• Description: Eval BD FOR MULTI CHANNEL 96KHz Codec
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1939AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1939
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 112dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UG-040
You can now open the Automated Register Window Builder
application and load the file for the part onto your evaluation
board.
POWERING THE BOARD
The AD1937/AD1939 evaluation board requires power supply
input of ±12 V dc and ground to the three binding posts; +12 V
draws ~250 mA, and −12 V draws ~100 mA. The on-board
regulators provide two 3.3 V rails and one 5.0 V rail. The 3.3 V
rails supply AVDD and DVDD for the AD1937/AD1939; DVDD
also supplies power for the peripheral active components on the
board. The 5.0 V rail provides voltage only to the AD1937/
AD1939 internal regulator, which consists of a PNP pass tran-
sistor and a few passive components. The PNP is driven into
3.3 V regulation by the VDRIVE pin of the AD1937/AD1939,
with the VSUPPLY and VSENSE pins acting as power and
feedback for the regulator. An appropriate sized PNP can supply
3.3 V to the AVDD and DVDD pins of the AD1937/AD1939.
The jumper blocks are shown in Figure 6 and Figure 7.
The first step in using the AD1937/AD1939 internal regulator is
to provide power to the regulator circuit by moving the AD1937/
AD1939 REG jumper from DISABLE to ENABLE, as shown in
Figure 7. Three discrete jumpers allow the AD1937/AD1939 to
be run from either the main AVDD and DVDD regulators or
the AD1937/AD1939 internal regulator. These jumpers also
allow measurement of current drawn by the individual sections
of the AD1937/AD1939. The only components on the AD1937/
AD1939 side of the jumper are the AD1937/AD1939 and the
supply decoupling capacitors.
MAIN REGS
MAIN REGS
193X REG
193X REG
Figure 7. AD1939 Internal Regulator Active
Figure 6. AD1939 Main Regulators Active
JP5
JP5
JP6 JP7
JP6 JP7
R117
C122
R117
C122
DISABLE
DISABLE
ENABLE
ENABLE
C96
C96
JP15
JP15
Q1
Q1
Rev. 0 | Page 4 of 32
SETTING UP THE MASTER CLOCK (MCLK)
The AD1937/AD1939 evaluation board has a series of jumpers
that give the user great flexibility in the MCLK clock source of
the AD1937/AD1939. MCLK can come from six different
sources: passive crystal, active oscillator, external clock in, S/PDIF
receiver, and two header connections. Note that the complex
programmable logic device (CPLD) on the board must have a
valid clock source; the frequency is not critical. These jumper
blocks can assign a clock to the CPLD as well. Most applications
of the board use MCLK from either the S/PDIF receiver or one
of the header (HDR) inputs. Figure 8 to Figure 10 show the on-
board active oscillator disabled so that it does not interfere with
the selected clock. The clock feed to the CPLD comes directly
from the clock source.
Note that, if the HDR connectors are to be driven with MCLK
from a source on the evaluation board, SW2 and/or SW3 must
be switched from the IN position to the OUT position.
OSC DISABLE
OSC DISABLE
Figure 8. S/PDIF Receiver as MCLK Master; the AD1939 and CPLD as Slaves
Figure 9. HDR1 as MCLK Master; the AD1939, CPLD, and HDR2 as Slaves
C158
C158
L7
L7
1938_MCLKI
1938_MCLKI
EXT
EXT
R160
R160
U21
U21
CPLD
HDR2
HDR1
HDR2
HDR1
CPLD
HDR2
HDR1
HDR2
HDR1
JP18
JP19
JP18
JP19
JP23
JP25
JP27
JP28
JP29
JP30
JP31
JP23
JP25
JP27
JP28
JP29
JP30
JP31
8416
8416
JP22
JP22
CLK
CLK
193X_MCLKI
193X_MCLKI
Evaluation Board User Guide
DISABLE
DISABLE
R174
R174
JP20
JP20
C168
C168
Y1
Y1
R167
R169
R172
R167
R169
R172
U22
U22
MCLKO
XTAL
MCLKO
XTAL
C170
C170
C147
U18
C147
U18
R175
R175
193X_MCLKO
193X_MCLKO
EXT CLK IN
EXT CLK IN
J22
J23
J22
J23