EVAL-AD1939AZ Analog Devices Inc, EVAL-AD1939AZ Datasheet
EVAL-AD1939AZ
Specifications of EVAL-AD1939AZ
Related parts for EVAL-AD1939AZ
EVAL-AD1939AZ Summary of contents
Page 1
FEATURES PLL generated or direct master clock Low EMI design 112 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24-bits and 8 kHz to ...
Page 2
AD1939 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Test Conditions ............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 4 Digital ...
Page 3
SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) 3 Temperature range As specified in Table 1 and Table 2 Master clock 12.288 ...
Page 4
AD1939 Parameter Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output REGULATOR Input Supply Voltage Regulated Output Voltage Specifications measured at a ...
Page 5
DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < T < +105°C, DVDD = 3.3 V ± 10%. A Table 4. Parameter High Level Input Voltage ( Low Level Input Voltage ( Input Leakage High Level Output Voltage (V ) ...
Page 6
AD1939 DIGITAL FILTERS Table 6. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay TIMING SPECIFICATIONS −40°C < ...
Page 7
Parameter SPI PORT t CCH t CCL f CCLK t CDS t CDH t CLS t CLH t CLHIGH t COE t COD t COH t COTS DAC SERIAL PORT t DBH t DBL t DLS t DLH t DLS ...
Page 8
AD1939 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Analog (AVDD) Digital (DVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute ...
Page 9
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND 1 MCLKI/XI 2 MCLKO/XO 3 AGND 4 AVDD 5 OL3P 6 OL3N 7 OR3P 8 OR3N 9 OL4P 10 OL4N 11 OR4P 12 OR4N 13 PD/RST 14 DSDATA4 15 DGND ...
Page 10
AD1939 Pin No. In/Out Mnemonic 25 O VDRIVE 26 I/O ASDATA2 27 O ASDATA1 28 I/O ABCLK 29 I/O ALRCLK 30 I CIN 31 I/O COUT 32 I DVDD 33 I DGND 34 I CCLK 35 I CLATCH 36 O ...
Page 11
TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0. FREQUENCY (kHz) Figure 3. ADC Pass-Band Filter Response, 48 kHz 0 –10 –20 –30 –40 –50 –60 –70 –80 ...
Page 12
AD1939 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (kHz) Figure 9. DAC Pass-Band Filter Response, 192 kHz 32 64 Rev Page –2 –4 –6 –8 –10 ...
Page 13
THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four analog-to-digital converter (ADC) channels in the AD1939 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 ...
Page 14
AD1939 master clock. In addition especially important that the clock signal not pass through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1939. In most cases, this induces clock ...
Page 15
POWER SUPPLY AND VOLTAGE REFERENCE The AD1939 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. To minimize noise pickup, these pins should be bypassed with 100 nF ceramic chip capacitors ...
Page 16
AD1939 Combining the AUX ADC and DAC modes results in a system configuration of 8 ADCs and 12 DACs. The system, then, con- sists of two external stereo ADCs, two external stereo DACs, Table 12. Pin Function Changes in TDM ...
Page 17
ALRCLK ABCLK DSDATA1 DAC L1 DAC R1 (TDM_IN) 4 ON-CHIP ADC CHANNELS ASDATA1 ADC L1 ADC R1 (TDM_OUT) 32 BITS MSB DLRCLK LEFT (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ALRCLK ABCLK 4 ON-CHIP ADC CHANNELS ...
Page 18
AD1939 ALRCLK ABCLK UNUSED SLOTS DSDATA1 EMPTY EMPTY EMPTY (TDM_IN) 4 ON-CHIP ADC CHANNELS ASDATA1 ADC L1 ADC R1 ADC L2 ADC R2 (TDM_OUT) DLRCLK (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ASDATA2 MSB (AUX1_OUT) DSDATA4 ...
Page 19
DAISY-CHAIN MODE The AD1939 also allows a daisy-chain configuration to expand the system to 8 ADCs and 16 DACs (see Figure 18). In this mode, the DBCLK frequency is 512 f . The first eight slots of the S DAC ...
Page 20
AD1939 DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 DAC L1 DAC R1 (IN) DSDATA2 (OUT) DSDATA3 DAC L3 DAC R3 (IN) DSDATA4 (OUT) 32 BITS MSB FIRST SECOND AD1939 AD1939 Figure 19. Dual-Line DAC ...
Page 21
ALRCLK ABCLK 4 ADC CHANNELS OF SECOND IC IN THE CHAIN ASDATA1 (TDM_OUT OF THE SECOND AD1939 ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2 IN THE CHAIN) ASDATA2 (TDM_IN OF THE ...
Page 22
AD1939 t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATAx LEFT-JUSTIFIED MSB MODE t DDH DSDATAx 2 I S-JUSTIFIED MODE DSDATAx RIGHT-JUSTIFIED MODE t ABH ABCLK t ABL t ALS ALRCLK t ABDD ASDATAx LEFT-JUSTIFIED MSB MODE ASDATAx ...
Page 23
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12) Pin Mnemonic Stereo Modes ASDATA1 ADC1 Data Out ASDATA2 ADC2 Data Out DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 ...
Page 24
AD1939 CONTROL REGISTERS DEFINITIONS The global address for the AD1939 is 0x04, shifted left one bit due to the R/ W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. ...
Page 25
Table 17. PLL and Clock Control 1 Register Bit Value Function 0 0 PLL clock 1 MCLK 1 0 PLL clock 1 MCLK 2 0 Enabled 1 Disabled 3 0 Not locked 1 Locked 7:4 0000 Reserved DAC CONTROL REGISTERS ...
Page 26
AD1939 Table 20. DAC Control 2 Register Bit Value Function 0 0 Unmute 1 Mute 2:1 00 Flat 01 48 kHz curve 10 44.1 kHz curve 11 32 kHz curve 4 Reserved ...
Page 27
ADC CONTROL REGISTERS Table 23. ADC Control 0 Register Bit Value Function 0 0 Normal 1 Power down 1 0 Off Unmute 1 Mute 3 0 Unmute 1 Mute 4 0 Unmute 1 Mute 5 0 ...
Page 28
AD1939 Table 25. ADC Control 2 Register Bit Value Function 0 0 50/50 (allows 32, 24, 20 bit clocks (BCLKs) per channel) 1 Pulse (32 BCLKs per channel Drive out on falling edge (DEF) 1 Drive ...
Page 29
ADDITIONAL MODES The AD1939 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM ...
Page 30
AD1939 APPLICATION CIRCUITS Typical application circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure ...
Page 31
... AD1939YSTZRL –40°C to +105°C AD1939WBSTZ –40°C to +105°C AD1939WBSTZ-RL –40°C to +105°C EVAL-AD1939AZ RoHS Compliant Part Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD1939W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models ...
Page 32
AD1939 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06071-0-9/10(C) Rev Page ...