EPF10K50VBC356-1 Altera, EPF10K50VBC356-1 Datasheet - Page 31

FLEX 10KA

EPF10K50VBC356-1

Manufacturer Part Number
EPF10K50VBC356-1
Description
FLEX 10KA
Manufacturer
Altera
Datasheet

Specifications of EPF10K50VBC356-1

Family Name
FLEX 10K
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# Registers
930
# I/os (max)
274
Frequency (max)
250MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
2880
Ram Bits
20480
Device System Gates
116000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
356
Package Type
BGA
Lead Free Status / Rohs Status
Not Compliant

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Altera Corporation
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices; it provides up to 12 peripheral control signals that
can be allocated as follows:
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, an LE in a different row can drive a column interconnect,
which causes a row interconnect to drive the peripheral control signal.
The chip-wide reset signal will reset all IOE registers, overriding any other
control signals.
Tables 8
rows that can drive global signals. These tables also show how the output
enable, clock enable, clock, and clear signals share 12 peripheral control
signals.
Up to eight output enable signals
Up to six clock enable signals
Up to two clock signals
Up to two clear signals
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
and
9
list the sources for each peripheral control signal, and the
31

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