DSPIC33EP512MU810-I/PT Microchip Technology, DSPIC33EP512MU810-I/PT Datasheet - Page 411

• Manufacturer Part Number: DSPIC33EP512MU810-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 536KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 25-5:
 2009-2011 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 15-7
bit 6-4
bit 3
bit 2-0
Note 1:
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
bit 15
bit 7
U-0
U-0
—
—
2:
3:
4:
See the Type C Timer Block Diagram
See the Type B Timer Block Diagram
See the PWM Module Register Interconnect Diagram
See the Oscillator System Diagram
Unimplemented: Read as ‘0’
CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = T5CLK
110 = T4CLK
101 = T3CLK
100 = T2CLK
011 = SYNCO2
010 = SYNCO1
001 = F
000 = F
CFLTREN: Comparator Filter Enable bit
1 = Digital filter enabled
0 = Digital filter disabled
CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
R/W-0
U-0
—
CMxFLTR: COMPARATOR FILTER CONTROL REGISTER
OSC
P
(4)
(4)
(1)
(2)
(1)
(2)
CFSEL<2:0>
W = Writable bit
‘1’ = Bit is set
(3)
(3)
R/W-0
U-0
—
(Figure
R/W-0
(Figure
(Figure
U-0
Preliminary
—
9-1).
13-1).
13-2).
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CFLTREN
R/W-0
U-0
—
(Figure
16-2).
R/W-0
U-0
—
CFDIV<2:0>
x = Bit is unknown
R/W-0
U-0
—
DS70616E-page 411
R/W-0
bit 8
bit 0
I-0
—