DAC1205D650HW/C1:5 NXP Semiconductors, DAC1205D650HW/C1:5 Datasheet - Page 12

• Manufacturer Part Number: DAC1205D650HW/C1:5
• Description: DAC1205D650HW/HTQFP100/TRAYBDP
• Manufacturer: NXP Semiconductors

Specifications of DAC1205D650HW/C1:5

• Settling Time: 20ns
• Number Of Bits: 12
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286777551

NXP Semiconductors
Table 5.
V
+85
specified.
[1]
[2]
[3]
[4]
DAC1205D650
Product data sheet
Symbol
IMD3
ACPR
NSD
DDA(1V8)
°
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 Ω and 120 Ω should
be connected across the pins (see
|V
and the inductance between the receiver and the driver circuit ground.
IMD3 rejection with −6 dBFS/tone.
C; typical values measured at T
gpd
| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
= V
Characteristics
DDD(1V8)
Parameter
third-order
intermodulation
distortion
adjacent channel
power ratio
noise spectral density f
= 1.8 V; V
…continued
DDA(3V3)
Figure
amb
Conditions
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
o1
s
o1
s
o1
s
o1
s
data
o
data
o
data
o
s
o
= V
= 25
= 320 Msps; 4× interpolation
= 320 Msps; 4× interpolation
= 640 Msps; 8× interpolation
= 640 Msps; 8× interpolation
= 640 Msps; 8× interpolation;
= 96 MHz
= 115.2 MHz
= 153.6 MHz
= 19 MHz at 0 dBFS
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
noise shaper disabled
noise shaper enabled
= 49 MHz; f
= 95 MHz; f
= 95 MHz; f
= 152 MHz; f
8).
All information provided in this document is subject to legal disclaimers.
DD(IO)(3V3)
= 76.8 MHz; f
= 153.6 MHz; f
= 153.6 MHz; f
°
C; R
Rev. 2 — 13 September 2010
L
= 50
Dual 12-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
= 3.3 V; AGND, DGND and GNDIO shorted together; T
o2
o2
o2
o2
= 51 MHz;
= 97 MHz;
= 97 MHz;
s
= 154 MHz;
Ω
s
s
= 614.4 Msps;
= 614.4 Msps;
= 614.4 Msps;
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
Test
[1]
C
C
I
C
I
C
C
C
C
C
C
C
C
C
C
[4]
[4]
[4]
[4]
Min
-
-
66
-
-
-
-
-
-
-
-
-
-
-
-
DAC1205D650
Typ
82
80
79
77
70
68
67
70
68
66
68
66
65
−149 -
−150 -
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
amb
=
−
dB
dB
dB
dB
dB
dB
Unit
dBc
dBc
dBc
dBc
dB
dB
dB
dBm/Hz
dBm/Hz
40
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°
C to