DAC1205D650HW/C1:5 NXP Semiconductors, DAC1205D650HW/C1:5 Datasheet - Page 11

• Manufacturer Part Number: DAC1205D650HW/C1:5
• Description: DAC1205D650HW/HTQFP100/TRAYBDP
• Manufacturer: NXP Semiconductors

Specifications of DAC1205D650HW/C1:5

• Settling Time: 20ns
• Number Of Bits: 12
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286777551

NXP Semiconductors
Table 5.
V
+85
specified.
DAC1205D650
Product data sheet
Symbol
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
I
V
N
Input timing (see
f
t
t
t
Output timing
f
t
NCO frequency range; f
f
f
Low-power NCO frequency range; f
f
f
Dynamic performance; PLL on
SFDR
SFDR
O(aux)
data
w(CLK)
h(i)
su(i)
s
s
NCO
step
NCO
step
DDA(1V8)
O(aux)
DAC(aux)mono
°
C; typical values measured at T
RBW
= V
Characteristics
DDD(1V8)
Parameter
auxiliary output
current
auxiliary output
voltage
auxiliary DAC
monotonicity
data rate
CLK pulse width
input hold time
input set-up time
sampling frequency
settling time
NCO frequency
step frequency
NCO frequency
step frequency
spurious-free
dynamic range
restricted bandwidth
spurious-free
dynamic range
Figure
= 1.8 V; V
s
10)
= 640 Msps
…continued
DDA(3V3)
amb
DAC
Conditions
differential outputs
compliance range
guaranteed
to ±0.5 LSB
register value = 00000000h
register value = FFFFFFFFh
register value = 00000000h
register value = F8000000h
f
B = f
f
B = f
f
B = f
f
0 dBFS; B = 30 kHz
f
0 dBFS; B = 1 MHz
Dual-port mode input
data
data
data
s
s
= V
= 25
= 640 Msps; f
= 640 Msps; f
f
f
2.51 MHz ≤ f
2.71 MHz ≤ f
3.51 MHz ≤ f
4 MHz ≤ f
o
o
All information provided in this document is subject to legal disclaimers.
= 640 MHz
= 4 MHz at 0 dBFS
= 19 MHz at 0 dBFS
DD(IO)(3V3)
= 80 MHz; f
= 80 MHz; f
= 160 MHz; f
data
data
data
°
C; R
/ 2; f
/ 2
/ 2; f
Rev. 2 — 13 September 2010
offset
L
o
o
= 50
= 35 MHz at 0 dBFS
= 70 MHz at 0 dBFS
Dual 12-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
= 3.3 V; AGND, DGND and GNDIO shorted together; T
offset
offset
offset
o
o
s
s
≤ 40 MHz
= 96 MHz at
= 96 MHz at
s
= 320 Msps;
= 640 Msps;
= 640 Msps;
Ω
≤ 2.71 MHz
≤ 3.51 MHz
≤ 4 MHz
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
Test
[1]
I
C
D
C
C
C
C
C
D
D
D
D
D
D
D
C
I
I
C
I
I
I
I
Min
-
0
-
-
1.5
1.1
1.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DAC1205D650
Typ
2.2
-
10
-
-
-
-
-
20
0
640
0.149 -
0
620
20
84
76
76
83
−91
−92
−93
−84
Max
-
2
-
160
T
-
-
650
-
-
-
-
-
-
-
-
-
-
−84
-
−85
−65
© NXP B.V. 2010. All rights reserved.
data
− 1.5 ns
amb
=
−
Unit
mA
V
bit
MHz
ns
ns
Msps
ns
MHz
MHz
Hz
MHz
MHz
MHz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
40
11 of 43
°
C to