CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 26

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-1. Oscillator Summary
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±7% at 62 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Phase-Locked
The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz.
Document Number: 001-53413 Rev. *L
MHzECO
kHzECO
Doubler
Source
IMO
DSI
PLL
ILO
Loop).
7
24 MHz
48 MHz
3-62 MHz
32 kHz
3 MHz
4 MHz
0 MHz
1 kHz
Fmin
IMO
Doubler for
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
48 MHz
USB
±1% over voltage and temperature
Crystal dependent
Input dependent
Input dependent
Input dependent
–50%, +100%
Crystal dependent
4-25 MHz
ECO
Tolerance at Fmin
24-67 MHz
PLL
External IO
0-66 MHz
Figure 6-1. Clocking Subsystem
or DSI
Clock Mux
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
System
32 kHz ECO
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler worksat input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
100 kHz
62 MHz
25 MHz
66 MHz
67 MHz
48 MHz
32 kHz
Fmax
1,33,100 kHz
ILO
±7%
Crystal dependent
Input dependent
Input dependent
Input dependent
–55%, +100%
Crystal dependent
7
Tolerance at Fmax
PSoC
CPU Clock Divider
Bus Clock Divider
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
16 bit
4 bit
®
3: CY8C36 Family
w
w
w
w
s
k
e
s
k
e
s
k
e
s
k
e
10 µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
Clock
CPU
Clock
Bus
Data Sheet
Startup Time
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