CY7C68034-56LTXC Cypress Semiconductor Corp, CY7C68034-56LTXC Datasheet - Page 13

• Manufacturer Part Number: CY7C68034-56LTXC
• Description: CY7C68034-56LTXC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56LTXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Processor Series: CY7C68xx
• Core: 8051
• Development Tools By Supplier: CY3684
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / Rohs Status: Compliant

Three Control OUT Signals
The NX2LP-Flex exposes three control signals, CTL[2:0]. CTLx
waveform edges can be programmed to make transitions as fast
as once per clock (20.8 ns using a 48 MHz clock).
Two Ready IN Signals
The 8051 programs the GPIF unit to test the RDY pins for GPIF
branching. The 56-pin package brings out two signals, RDY[1:0].
Long Transfer Mode
In GPIF master mode, the 8051 appropriately sets GPIF
transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,
or GPIFTCB0) for unattended transfers of up to 2
The GPIF automatically throttles data flow to prevent underflow
or overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
ECC Generation
The NX2LP-Flex can calculate error correcting codes (ECCs) on
data that passes across its GPIF or slave FIFO interfaces. There
are two ECC configurations:
■
■
The following two ECC configurations are selected by the ECCM
bit. The ECC can correct any one-bit error or detect any two-bit
error.
ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of data.
This configuration conforms to the SmartMedia Standard and is
used by both the NAND boot logic and default NAND firmware
image.
Document Number: 001-04247 Rev. *H
Note
2. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
Two ECCs, each calculated over 256 bytes (SmartMedia
Standard)
One ECC calculated over 512 bytes.
[2]
32
transactions.
When any value is written to ECCRESET and data is then
passed across the GPIF or slave FIFO interface, the ECC for the
first 256 bytes of data is calculated and stored in ECC1. The ECC
for the next 256 bytes of data is stored in ECC2. After the second
ECC is calculated, the values in the ECCx registers do not
change until ECCRESET is written again, even if more data is
subsequently passed across the interface.
ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data.
When any value is written to ECCRESET and data is then
passed across the GPIF or slave FIFO interface, the ECC for the
first 512 bytes of data is calculated and stored in ECC1; ECC2
is unused. After the ECC is calculated, the value in ECC1 does
not change until ECCRESET is written again, even if more data
is subsequently passed across the interface
Autopointer Access
NX2LP-Flex provides two identical autopointers. They are
similar to the internal 8051 data pointers, but with an additional
feature: they can optionally increment after every memory
access. Also, the autopointers can point to any NX2LP-Flex
register or endpoint buffer space.
I
NX2LP has one I
control external I
mode only. The I
for use after the initial NAND access.
I
The I
resistors even if no EEPROM is connected to the NX2LP.
I
The 8051 can control peripherals connected to the I
the I
control only and is never an I
2
2
2
C Port Pins
C Interface General-Purpose Access
C Controller
2
2
CTL and I
C pins SCL and SDA must have external 2.2-kΩ pull up
2
2
2
C post is disabled at startup and only available
DATA registers. NX2LP provides I
2
C devices. The I
C port that the 8051, once running uses to
CY7C68033, CY7C68034
2
C slave.
2
C port operates in master
Page 13 of 38
2
C bus using
2
C master
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