CY7C68034-56LTXC Cypress Semiconductor Corp, CY7C68034-56LTXC Datasheet - Page 11

• Manufacturer Part Number: CY7C68034-56LTXC
• Description: CY7C68034-56LTXC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56LTXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Processor Series: CY7C68xx
• Core: 8051
• Development Tools By Supplier: CY3684
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / Rohs Status: Compliant

Endpoint RAM
Size
■
■
Organization
■
■
■
For high speed endpoint configuration options, see
Default Full Speed Alternate Settings
Table 6. Default Full Speed Alternate Settings
1. ‘0’ means ‘not implemented.’
2. ‘2×’ means ‘double buffered.’
Document Number: 001-04247 Rev. *H
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
3 × 64 bytes
8 × 512 bytes
EP0
❐
EP1IN, EP1OUT
❐
EP2,4,6,8
❐
❐
Bidirectional endpoint zero, 64-byte buffer
64-byte buffers, bulk or interrupt
Eight 512-byte buffers, bulk, interrupt, or isochronous.
EP4 and EP8 can be double buffered, while EP2 and 6 can
be either double, triple, or quad buffered.
Alternate Setting
(Endpoints 0 and 1)
(Endpoints 2, 4, 6, 8)
EP0 IN&OUT
EP1 OUT
EP1 IN
EP8
EP2
EP4
EP6
512
512
512
512
512
512
512
512
1
64
64
64
64
0
0
0
0
0
0
0
EP4
EP2
EP6
512
512
512
512
512
512
512
512
64
64
64
2
64
64 bulk
64 bulk
64 bulk out (2×)
64 bulk out (2×)
64 bulk in (2×)
64 bulk in (2×)
EP2
EP4
EP6
1024
1024
512
512
512
512
64
64
64
3
Figure 8. Endpoint Configuration
[1, 2]
Figure
EP2
EP8
EP6
512
512
512
512
512
512
512
512
64
64
64
4
1
EP2
EP6
512
8.
512
512
512
512
512
512
512
64
64
64
5
EP2
EP6
1024
1024
512
512
512
512
64
64
64
6
Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
Endpoint Configurations (High Speed Mode)
Endpoints 0 and 1 are the same for every configuration. Endpoint
0 is the only control endpoint, and endpoint 1 can be either bulk
or interrupt. The endpoint buffers can be configured in any 1 of
the 12 configurations shown in the vertical columns. When
operating in full speed bulk mode, only the first 64 bytes of each
buffer are used. For example, in high speed the max packet size
is 512 bytes, but in full speed it is 64 bytes. Even though a buffer
is configured to be a 512 byte buffer, in full speed only the first
64 bytes are used. The unused endpoint buffer space is not
available for other operations. The following is an example
endpoint configuration:
EP2–1024 double buffered; EP6–512 quad buffered (column 8
in
64
64 int
64 int
64 int out (2×)
64 bulk out (2×)
64 int in (2×)
64 bulk in (2×)
Figure
EP2
EP6
EP8
1024
1024
512
512
512
512
64
64
64
7
8).
EP2
1024
1024
EP6
512
512
512
64
64
64
512
8
2
EP2
EP6
1024
1024
1024
1024
64
64
64
9
CY7C68033, CY7C68034
EP2
EP6
EP8
512
512
512
512
512
512
512
512
64
64
64
10
EP2 EP2
1024
EP8
1024
1024
1024
512
64
64 int
64 int
64 iso out (2×)
64 bulk out (2×)
64 iso in (2×)
64 bulk in (2×)
64
64
64
512
11
1024
1024
1024
1024
12
64
64
64
3
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