CY7C68034-56LTXC Cypress Semiconductor Corp, CY7C68034-56LTXC Datasheet

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... Uses external clock or asynchronous strobes ❐ Easy interface to ASIC and DSP ICs ❐ Available in space saving 56-pin QFN package ■ CY7C68034 Only Silicon Features Ideal for battery powered applications ■ Suspend current: 100 μA (typ) ❐ CY7C68033 Only Silicon Features Ideal for non-battery powered applications ■ ...

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... Industry standard ECC NAND Flash correction ■ 1 bit for every 256-bit correction ❐ 2-bit error detection ❐ Document Number: 001-04247 Rev. *H CY7C68033, CY7C68034 Industry standard (SmartMedia) page management for wear ■ leveling algorithm, bad block handling, and physical to logical management. 8-bit NAND Flash interface support ■ ...

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... Contents CY7C68033/CY7C68034 Silicon Features .............................. 1 CY7C68034 Only Silicon Features .................................... 1 CY7C68033 Only Silicon Features .................................... 1 Logic Block Diagram ............................................................... 1 Default NAND Firmware Features ..................................... 2 Contents ................................................................................... 3 Acronyms ................................................................................. 3 Overview ................................................................................... 4 Applications ............................................................................. 4 Functional Overview ............................................................... 4 USB Signaling Speed ........................................................ 4 8051 Microprocessor ......................................................... 4 I2C Bus .............................................................................. 5 Buses ................................................................................. 6 Enumeration ....................................................................... 6 Default Silicon ID Values ................................................... 7 ReNumeration .................................................................... 7 Bus-powered Applications ................................................. 7 Interrupt System ................................................................. 7 Reset and Wakeup ...

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... Overview Cypress Semiconductor Corporation’s EZ-USB (CY7C68033/CY7C68034 firmware-based, programmable version of the EZ-USB NX2LP (CY7C68023/CY7C68024), which is a fixed-function, low power USB 2.0 NAND Flash controller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a program- mable peripheral interface in a single chip, Cypress has created a very cost-effective solution that enables feature-rich NAND Flash-based applications ...

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... PLL 12-pF capacitor values assumes a trace capacitance per side on a four-layer FR4 PCA Document Number: 001-04247 Rev. *H CY7C68033, CY7C68034 Special Function Registers Certain 8051 SFR addresses are populated to provide fast access to critical NX2LP-Flex functions. These SFR additions are shown in Table 1 on page 6 ...

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... Ax Bx IOC IOD INT2CLR IOE INT4CLR OEA OEB OEC OED OEE IE IP EP2468STAT EP01STAT EP24FIFOFLGS GPIFTRIG EP68FIFOFLGS GPIFSGLDATH GPIFSGLDATLX AUTOPTRSETUP GPIFSGLDATLNOX and Manufacturing Mode on page 7. CY7C68033, CY7C68034 SCON1 PSW ACC B SBUF1 T2CON EICON EIE EIP RCAP2L RCAP2H TL2 TH2 Page [+] Feedback ...

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... EZ-USB microcontrollers. This is due to the additional NAND boot logic that is present in the NX2LP-Flex ROM space. Also, these values are fixed and cannot be changed in the firmware. CY7C68033, CY7C68034 Default VID/PID/DID 0x04B4 Cypress Semiconductor ® 0x8613 EZ-USB ...

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... Bus errors exceeded the programmed limit Reserved Reserved Reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error CY7C68033, CY7C68034 Notes Table 4 shows the priority and Page [+] Feedback ...

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... This pin has hysteresis and is active LOW. When a crystal is RESET RESET Power-on Reset Note 1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 μs. Document Number: 001-04247 Rev. *H Source EP2PF Endpoint 2 programmable flag EP4PF Endpoint 4 programmable flag EP6PF ...

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... Figure 7. Internal Register Addresses FFFF F000 EFFF E800 E7FF E7C0 E740 E700 E6FF E4FF E47F E400 E1FF CY7C68033, CY7C68034 FFFF 7.5 kBytes USB registers and 4 kBytes FIFO buffers (RD#, WR#) E200 E1FF 512 Bytes RAM Data (RD#, WR#)* E000 3FFF 15 kBytes RAM Code and Data ...

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... CY7C68033, CY7C68034 EP2 EP2 EP2 EP2 512 1024 1024 512 1024 512 EP6 ...

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... The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, and so on. A sequence of the GPIF vectors make up a single waveform that is executed to perform the desired data move between the NX2LP-Flex and the external device. CY7C68033, CY7C68034 int 64 int 512 iso out (2× ...

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... EEPROM is connected to the NX2LP Interface General-Purpose Access The 8051 can control peripherals connected to the the I CTL and I DATA registers. NX2LP provides I control only and is never an I CY7C68033, CY7C68034 2 C port operates in master 2 C bus using 2 C master 2 C slave. Page [+] Feedback ...

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... PA1/INT1# PA1/INT1# ↔ ↔ PA0/INT0# PA0/INT0# ↔ ↔ GPIO8 GPIO8 ← ← GPIO9 GPIO9 CY7C68033, CY7C68034 Default NAND Firmware Use ↔ CE7#/GPIO7 ↔ CE6#/GPIO6 ↔ CE5#/GPIO5 ↔ CE4#/GPIO4 ↔ CE3#/GPIO3 ↔ CE2#/GPIO2 ↔ ...

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... Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment RDY0/*SLRD 1 RDY1/*SLWR 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 GPIO8 13 RESERVED# 14 Document Number: 001-04247 Rev. *H CY7C68033, CY7C68034 RESET# 42 GND 41 PA7/*FLAGD/SLCS# 40 PA6/*PKTEND 39 PA5/FIFOADR1 38 PA4/FIFOADR0 37 PA3/*WU2 36 PA2/*SLOE 35 PA1/INT1# ...

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... RE0 NAND read enable output signal. O/Z H Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. RE1 NAND read enable output signal. CY7C68033, CY7C68034 Description Page [+] Feedback ...

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... WP_NF# is the NAND write-protect control output signal. I/O/Z I Multiplexed pin whose function is selected by IFCONFIG[1:0]. (PA5) PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. WP_SW# is the NAND write-protect switch input signal. CY7C68033, CY7C68034 Description Page [+] Feedback ...

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... FD[7] is the bidirectional FIFO/GPIF data bus. DD7 is a bidirectional NAND data bus signal. I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] (PD0) and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. CE0 NAND chip enable output signal. CY7C68033, CY7C68034 Description Page [+] Feedback ...

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... Power N/A Analog V . Connect this pin to 3.3V power source. This signal CC provides power to the analog section of the chip. Ground N/A Analog Ground. Connect to ground with as short a path as possible. Power N Connect to 3.3V power source. CC Ground N/A Ground. CY7C68033, CY7C68034 Description Page [+] Feedback ...

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... PL7 PL6 PL5 PL4 PL3 PL7 PL6 PL5 PL4 PL3 PL7 PL6 PL5 PL4 PL3 CY7C68033, CY7C68034 Default Access xxxxxxxx RW reserved reserved reserved 00000000 R CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGC2 FLAGC1 FLAGC0 00000000 RW ...

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... EDGEPF EDGEPF EP8 EP6 EP4 0 0 EP8 EP6 EP4 EP8 EP6 EP4 EP2 EP1 CY7C68033, CY7C68034 Default Access 00000000 W LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 00000000 R COL0 LINE17 LINE16 00000000 R LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 00000000 R COL0 0 0 ...

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... BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 CY7C68033, CY7C68034 Default Access EP0 0 IBN xxxxxx0x bbbbbbrb SUTOK SOF SUDAV 00000000 RW SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb EP1IN EP0OUT EP0IN 00000000 RW EP1IN EP0OUT EP0IN 0 RW ...

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... CTL0E0/ CTL3 CTL5 CTL4 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE 0 SLAVE RDYASYNC CTLTOGL SUSTAIN CY7C68033, CY7C68034 Default Access 0 BUSY STALL 10000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb EMPTY 0 STALL 00101000 rrrrrrrb EMPTY ...

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... DISCON CY7C68033, CY7C68034 Default Access 00000010 RW TC26 TC25 TC24 00000000 RW TC18 TC17 TC16 00000000 RW TC10 TC9 TC8 00000000 RW TC2 TC1 TC0 00000001 RW 00000000 RW 0 FS1 FS0 00000000 FIFO2FLAG 00000000 xxxxxxxx W 0 FS1 FS0 00000000 FIFO4FLAG 00000000 xxxxxxxx W 0 FS1 FS0 00000000 RW ...

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... PS1 PT2 PS0 PT1 DONE D15 D14 D13 D12 D11 CY7C68033, CY7C68034 Default Access A10 A9 A8 00000000 00000000 RW A10 A9 A8 00000000 SEL 00000000 IDLE 00110000 RW IT1 IE0 IT0 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 RW D10 D9 D8 00000000 RW MD2 MD1 MD0 ...

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... RCLK TCLK EXEN2 D15 D14 D13 D12 D11 RS1 RS0 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C68033, CY7C68034 Default Access xxxxxxxx R RB8_1 TI_1 RI_1 00000000 00000000 RW TR2 CT2 CPRL2 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 00000000 01000000 00000000 RW EX4 EI² ...

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... OUT I = –4 mA OUT Except D+/D– D+/D– Connected Disconnected Connected Disconnected 8051 running, connected to USB HS 8051 running, connected to USB FS Before bMaxPower granted by host V min = 3 CY7C68033, CY7C68034 Min Typ Max Unit 3.00 3.3 3.60 V μs 200 2 5.25 V –0.5 0 5.25 V –0.5 ...

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... MHz IFCLK. x Notes 5. Dashed lines denote signals with programmable polarity. Document Number: 001-04247 Rev RDpwh t RDpwl t XFLG t XFD N OEon OEoff [1] Description Min t WRpwh t WRpwl t t FDH SFD t XFD Description Min CY7C68033, CY7C68034 [5] Max Unit 10.5 ns 10.5 ns [5] [1] Max Unit Page [+] Feedback ...

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... FIFOADR[1:0] to FIFODATA output propagation delay XFD Document Number: 001-04247 Rev PEpwh t PEpwl t XFLG [1] Description Min t OEoff t OEon Description Min t XFLG t XFD N N+1 Description Min CY7C68033, CY7C68034 [2] Max Unit 115 ns [5] Max Unit 10.5 ns 10.5 ns [5] Max Unit 10.7 ns 14.3 ns Page [+] Feedback ...

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... RDpwl RDpwh RDpwl T=2 T=3 T=4 T XFD XFD N N+1 t OEon T=1 SLRD SLOE SLOE SLRD N N+1 N+1 N+1 N Not Driven N N+1 CY7C68033, CY7C68034 [5] Max Unit [5] t FAH RDpwl RDpwh RDpwh T=6 t XFLG t XFD N+3 N+2 t OEoff T=7 SLRD SLRD SLRD SLOE ...

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... SLWR and the PKTEND signal before the SFD at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de-asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. CY7C68033, CY7C68034 Figure 17, data N [5] t FAH t ...

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... Ordering Information Ordering Code Silicon for battery-powered applications CY7C68034-56LTXC Silicon for non-battery-powered applications CY7C68033-56LTXC Development Kit CY3686 Ordering Code Definitions Document Number: 001-04247 Rev. *H CY7C68033, CY7C68034 Description mm, 56 QFN (Sawn mm, 56 QFN (Sawn) EZ-USB NX2LP-Flex Development Kit Page [+] Feedback ...

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... Package Diagram Document Number: 001-04247 Rev. *H Figure 20. 56-Pin QFN LF56A CY7C68033, CY7C68034 51-85144 *H Page [+] Feedback ...

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... Document Number: 001-04247 Rev. *H Figure 21. 56-Pin QFN ( 0.9 MM) - Sawn CY7C68033, CY7C68034 001-53450 *B Page [+] Feedback ...

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... Note 6. Source for recommendations: EZ-USB FX2™PCB Design Recommendations Document Number: 001-04247 Rev. *H CY7C68033, CY7C68034 Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the printed circuit board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB ...

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... X-Ray image of the assembly (darker areas indicate solder). 0.017” dia Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane. Figure 24. X-ray Image of the Assembly CY7C68033, CY7C68034 Page [+] Feedback ...

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... Changed IFCLK and CLKOUT pins to GPIO8 and GPIO9. Removed external IFCLK DPT Added 56 QFN ( mm) package diagram and added CY7C68033-56LTXC and CY7C68034-56LTXC part information in the Ordering Information table Updated revision in the footer ODC Removed inactive parts.Updated package diagram. Added table of contents.Updated links in Sales, Solutions and Legal Information. ...

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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-04247 Rev. *H All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised May 18, 2010 CY7C68033, CY7C68034 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...