CY7C4265-15AXC Cypress Semiconductor Corp, CY7C4265-15AXC Datasheet - Page 13

• Manufacturer Part Number: CY7C4265-15AXC
• Description: IC,FIFO,16KX18,SYNCHRONOUS,CMOS,QFP,64PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4265-15AXC

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2171; CY7C4265-15AXC

Switching Waveforms
Document #: 38-06004 Rev. *G
Notes
29. If a write is performed on this rising edge of the write clock, there are Full − (m − 1) words of the FIFO when PAF goes LOW.
30. PAF offset = m.
31. t
RCLK and the rising edge of WCLK is less than t
SKEW3
D
WCLK
WCLK
WEN2
RCLK
0
WEN
WEN
REN
–D
PAF
LD
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of
17
Figure 13. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
t
t
CLKH
CLKH
FULL– M + 1 WORDS
(continued)
t
CLK
t
t
ENS
ENS
t
IN FIFO
DS
PAE OFFSET
t
t
ENS
ENS
Figure 14. Write Programmable Registers
SKEW3
t
t
ENH
ENH
, then PAF may not change state until the next WCLK rising edge.
t
t
CLKL
CLKL
t
ENH
t
DH
Note
Note
30
PAF OFFSET
29
t
PAF
t
ENS
t
SKEW3
FULL– M WORDS
IN FIFO
t
[31]
ENS
PAE OFFSET
D
0
[27]
– D
t
ENH
11
t
PAF synch
CY7C4265
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