CY7C4265-15AXC Cypress Semiconductor Corp, CY7C4265-15AXC Datasheet - Page 3

• Manufacturer Part Number: CY7C4265-15AXC
• Description: IC,FIFO,16KX18,SYNCHRONOUS,CMOS,QFP,64PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4265-15AXC

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2171; CY7C4265-15AXC

Pin Configurations
Pin Description
The CY7C4265 provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full. The Half Full flag shares the WXO
pin. This flag is valid in the standalone and width-expansion
configurations. In the depth expansion, this pin provides the
expansion out (WXO) information that is used to signal the next
FIFO when it is activated.
The Empty and Full flags are synchronous, that is, they change
state relative to either the Read Clock (RCLK) or the Write Clock
Table 1. Selection Guide
Table 2. Density and Package
Document #: 38-06004 Rev. *G
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
) (mA)
Description
Description
Package
Density
Commercial
Industrial
Figure 1. 64-Pin TQFP/STQFP (Top View)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
7C4255/65-10
100
0.5
10
45
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8
3
8
64-pin TQFP, STQFP
CY7C4265
16K x18
CY7C4265
7C4255/65/65A-15
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags remain valid from one clock
cycle to the next. The Almost Empty/Almost Full flags become
synchronous if the V
tions are fabricated using an advanced 0.5μ CMOS
technology. Input ESD protection is greater than 2001V, and
latch up is prevented by the use of guard rings.
66.7
10
15
10
45
50
4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CC
7C4255/65-25
/SMODE is tied to V
40
15
25
15
45
50
Q
Q
GND
Q
Q
V
Q
Q
GND
Q
Q
Q
Q
GND
Q
V
6
1
CC
CC
14
13
12
11
10
9
8
7
6
5
4
SS
7C4255/65-35
CY7C4265
. All configura-
28.6
20
35
20
45
50
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