CY7C4265-15ASC Cypress Semiconductor Corp, CY7C4265-15ASC Datasheet

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... RS FL/RT WXI WXO/HF RXI RXO Note 1. CY7C4265 and CY7C4265A are functionally identical Cypress Semiconductor Corporation Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A 8K/16K x 18 Deep Sync FIFOs Functional Description The CY7C4255/65/65A are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. ...

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... Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Commercial Current (I ) (mA) Industrial CC1 Table 2. Density and Package Description Density Package Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A ...

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... I CC Almost Empty/ Almost Full Flags Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Function Data inputs for an 18-bit bus. Enables the WCLK input. Enables the RCLK input. The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. ...

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... CC 8. Tested initially and after any design changes that may affect these parameters. 9. Tested initially and after any process changes that may affect these parameters. Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Output Current into Outputs (LOW)............................. 20 mA [2] Static Discharge Voltage............................................ >2001V (per MIL– ...

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... CC t Clock to Programmable Almost-Full Flag PAEsynch (Synchronous mode, V /SMODE tied Clock to Half-Full Flag HF t Clock to Expansion Out XO Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A [10, 11] ALL INPUT PULSES 3.0V 10% GND ≤ Equivalent to: THÉ VENIN EQUIVALENT 410Ω OUTPUT 7C42X5, 7C42X5-10 7C4265A-15 ...

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... AC parameters except for t L OHZ 11 for OHZ 12. Pulse widths less than minimum values are not enabled. 13. Values guaranteed by design, not currently tested. 14 after program register write is not be valid until PAFasynch PAEasynch Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A 7C42X5, 7C42X5-10 7C4265A-15 Min Max Min 4.5 6 ...

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... WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time SKEW2 between the rising edge of WCLK and the rising edge of RCLK is less than t Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Figure 3. Write Cycle Timing t CLK ...

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... When t > minimum specification, t (maximum SKEW2 FRL The Latency Timing applies only at the Empty Boundary (EF = LOW). CLK SKEW2 20. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A [17] Figure 5. Reset Timing RSR t RSF t RSF t RSF ...

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... SKEW1 D – WFF FF WEN RCLK t ENH t ENS REN LOW DATA IN OUTPUT REGISTER Q – Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Figure 7. Empty Flag Timing ENS t t REF REF t A Figure 8. Full Flag Timing [15 SKEW1 DATA WRITE t WFF t ENS DATA READ D1 t ENH ...

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... REN Figure 10. Programmable Almost Empty Flag Timing t CLKH WCLK WEN [21] PAE RCLK REN Note 21. PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Figure 9. Half-Full Flag Timing t CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE t ...

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... If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW. 25. PAF offset = m. Number of data words written into FIFO already = 8192 − for the CY7C4255 and 16384 − for the CY7C4265/65A. 26. PAF is offset = m. ...

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... RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of SKEW3 RCLK and the rising edge of WCLK is less than t Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Note 29 t CLKL ...

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... CLKH WCLK RXO t ENS REN WXI t XIS WCLK Notes 32. Write to Last Physical Location. 33. Read from Last Physical Location. Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Figure 15. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET Figure 16. Write Expansion Out Timing Note Note 32 ...

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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at t 36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Figure 19. Read Expansion In Timing t [34, 35, 36] Figure 20 ...

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... Note 37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. ...

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... Notes 38 Empty Offset (Default Values: CY7C4255/CY7C4265/65A n = 127). 39 Full Offset (Default Values: CY7C4255/CY7C4265/65A n = 127). Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t after the retransmit pulse ...

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... The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A RESET (RS) 18 7C4255 ...

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... Figure 22. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion DATA IN(D) WRITE CLOCK(WCLK) WRITE ENABLE(WEN) RESET (RS) LOAD (LD) FF PAF FIRST LOAD (FL) Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Configuration WXO RXO 7C4255 7C4265 PAF PAE WXI RXI WXO RXO ...

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... SUPPLY VOLTAGE 1.40 1.20 1. 3. 25° MHz 0.60 4.00 4.50 5.00 5.50 6.00 SUPPLY VOLTAGE (V) Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Figure 23. Typical AC and DC Characteristics NORMALIZED t vs. SUPPLY A TEMPERATURE 1.60 1.40 1.20 1. 25° 0.60 −55.00 5.00 5.50 6.00 AMBIENT TEMPERATURE (° ...

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... Ordering Code 10 CY7C4265–10AC CY7C4265–10ASC CY7C4265–10ASXC CY7C4265–10AI CY7C4265–10AXI 15 CY7C4265–15AC CY7C4265–15AXC CY7C4265-15ASC CY7C4265A–15ASI Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A Package Package Name Type 51-85046 64-Pin Thin Quad Flatpack 51-85046 64-Pin Thin Quad Flatpack (Pb-free) ...

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... Package Diagrams Figure 24. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85051 Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A 51-85051 *A Page [+] Feedback [+] Feedback ...

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... Package Diagrams (continued) Figure 25. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85046 Document #: 38-06004 Rev. *E CY7C4255, CY7C4265, CY7C4265A 51-85046-*B 51-85046-*B Page [+] Feedback [+] Feedback ...

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... Document History Page Document Title: CY7C4255, CY7C4265, CY7C4265A 8K/16K X 18 Deep Sync FIFOs Document Number: 38-06004 Orig. of Submission REV. ECN NO. Change ** 106465 SZV *A 122257 RBI *B 252889 YDT *C 385985 ESH *D 2623658 VKN/PYRS *E 2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams ...