CY7C4265-10AXI Cypress Semiconductor Corp, CY7C4265-10AXI Datasheet
CY7C4265-10AXI
Specifications of CY7C4265-10AXI
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CY7C4265-10AXI Summary of contents
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... FIFO on each cycle. The output port is controlled in a similar manner by a free-running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C4265 have an Output Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... Document #: 38-06004 Rev. *G Empty Flag ................................................................ 16 Programmable Almost Empty/Almost Full Flag ......... 16 Retransmit ....................................................................... 17 Width Expansion Configuration .................................... 18 Depth Expansion Configuration (with Programmable Flags) ........................................... 18 Ordering Information ...................................................... 21 Ordering Code Definitions ......................................... 21 Package Diagrams .......................................................... 22 Document History Page ................................................. 24 Sales, Solutions, and Legal Information ...................... 25 Products .................................................................... 25 PSoC Solutions ......................................................... 25 CY7C4265 Page [+] Feedback ...
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... Pin Configurations Figure 1. 64-Pin TQFP/STQFP (Top View) Pin Description The CY7C4265 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full. The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations ...
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... When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4265 /SMODE is tied ...
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... Max. –10 +10 , –10 +10 IH < V < Commercial 45 Industrial 50 Commercial 10 Industrial 15 Test Conditions = 25° MHz, = 5.0V CY7C4265 Ambient [3] Temperature ± 10% 0°C to +70°C 5V ± 10% –40°C to +85°C 7C42X5, 7C42X5-25 7C42X5-35 7C4265A-15 Min Max Min Max Min Max 2.4 2.4 2.4 ...
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... ALL INPUT PULSES 3.0V 10% GND ≤ Equivalent to: THÉ VENIN EQUIVALENT 410Ω OUTPUT 7C42X5, 7C42X5-10 7C4265A-15 Min Max Min 100 4 [12 [13 [13 [14 CY7C4265 90% 90% 10% ≤ 1.91V Unit 7C42X5-25 7C42X5-35 Max Min Max Min Max 66.7 40 28.6 MHz ...
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... Pulse widths less than minimum values are not enabled. 13. Values guaranteed by design, not currently tested. 14 after program register write is not be valid until PAFasynch PAEasynch Document #: 38-06004 Rev. *G 7C42X5, 7C42X5-10 7C4265A-15 Min Max Min 6 4.5 6 PAF(E) CY7C4265 Unit 7C42X5-25 7C42X5-35 Max Min Max Min Max ...
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... Figure 4. Read Cycle Timing t CLK t CLKL NO OPERATION t REF VALID DATA t OE [16] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4265 NO OPERATION t WFF REF t OHZ Page [+] Feedback ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06004 Rev. *G [17] Figure 5. Reset Timing RSR t RSF t RSF t RSF [19] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4265 [18 [20 (maximum) = either 2 FRL CLK SKEW2 Page [+] Feedback ...
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... Document #: 38-06004 Rev. *G Figure 7. Empty Flag Timing ENS t t REF REF t A Figure 8. Full Flag Timing [15 SKEW1 DATA WRITE t WFF t ENS DATA READ CY7C4265 D1 t ENH [19] t FRL t t REF SKEW2 D0 NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ Page [+] Feedback ...
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... PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06004 Rev. *G Figure 9. Half-Full Flag Timing t CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE t ENS t CLKL t t ENS ENH t PAE WORDS IN FIFO t ENS CY7C4265 HALF FULLOR LESS WORDS IN FIFO t PAE Page [+] Feedback ...
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... If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW. 25. PAF offset = m. Number of data words written into FIFO already = 8192 − for the CY7C4255 and 16384 − for the CY7C4265/65A. 26. PAF is offset = m. ...
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... PAF ENH t SKEW3 t ENS Figure 14. Write Programmable Registers t CLKL t ENH t DH PAF OFFSET , then PAF may not change state until the next WCLK rising edge. SKEW3 CY7C4265 FULL– M WORDS [27] IN FIFO t [31] PAF synch t t ENS ENH PAE OFFSET – ...
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... Read from Last Physical Location. Document #: 38-06004 Rev. *G Figure 15. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET Figure 16. Write Expansion Out Timing Note Note Figure 17. Read Expansion Out Timing Note Figure 18. Write Expansion In Timing t XI CY7C4265 PAF OFFSET PAE OFFSET Page [+] Feedback ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at t 36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06004 Rev. *G Figure 19. Read Expansion In Timing t [34, 35, 36] Figure 20. Retransmit Timing t PRT to update these flags. RTR CY7C4265 t XI XIS t RTR . RTR Page [+] Feedback ...
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... The CY7C4256/65 consists of an array of 8K/16K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4265 also includes the control signals WXI, RXI, WXO, RXO for depth expansion. ...
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... L Notes 38 Empty Offset (Default Values: CY7C4265 n = 127). 39 Full Offset (Default Values: CY7C4265 n = 127). Document #: 38-06004 Rev. *G pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer ...
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... Width Expansion Configuration The CY7C4265 can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags of every FIFO ...
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... Document #: 38-06004 Rev. *G Configuration WXO RXO 7C4255 7C4265 PAF PAE WXI RXI WXO RXO 7C4255 7C4265 PAF PAE WXI RXI READ CLOCK(RCLK) WXO RXO READ ENABLE(REN) 7C4255 7C4265 OUTPUT ENABLE(OE PAE PAF WXI RXI CY7C4265 DATA OUT (Q) EF PAE Page [+] Feedback ...
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... AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 −55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE (°C) CY7C4265 vs. AMBIENT A = 5.0V 5.00 65.00 125.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1.25 1. 5. 25° 3.0V IN ...
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... Thin Quad Flatpack (Pb-free) 51-85046 64-Pin Thin Quad Flatpack (Pb-free) Temperature Grade Commercial Industrial Pb-free (RoHS Compliant) Package TQFP STQFP Speed grade x18 Depth Width: x18 FIFO Technology: CMOS Family: Dual-port SRAM Company ID Cypress CY7C4265 Operating Range Commercial Industrial Commercial Page [+] Feedback ...
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... Package Diagrams Figure 24. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85051 Document #: 38-06004 Rev. *G CY7C4265 51-85051 *B Page [+] Feedback ...
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... Figure 25. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85046 Document #: 38-06004 Rev. *G CY7C4265 51-85046 *D Page [+] Feedback ...
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... Power up requirements added to Maximum Ratings Information See ECN Removed PLCC package and pruned parts from Order Information See ECN Added Pb-Free logo to top of first page Added CY7C4265-10ASXC, CY7C4265-10AXI, CY7C4265-15AXC, CY7C4255-10AXC, CY7C4255-15AXC to ordering information 12/17/08 Added CY7C4265A part Updated Ordering information table ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06004 Rev. *G All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised November 24, 2010 CY7C4265 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...