CY7C1480V33-167AXC Cypress Semiconductor Corp, CY7C1480V33-167AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1480V33-167AXC
• Description: CY7C1480V33-167AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480V33-167AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2169; CY7C1480V33-167AXC

Document Number: 38-05283 Rev. *J
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides
a two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed
to support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
ZZ Mode Electrical Characteristics
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
into
X
the
) are asserted active to conduct a Write to the
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to Sleep current
ZZ Inactive to exit Sleep current
address
1
, CE
2
register
, CE
Description
3
are all asserted active,
and
the
address
ZZ > V
ZZ < 0.2V
ZZ > V
This parameter is sampled
This parameter is sampled
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected before entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table
(MODE = GND)
Address
Address
Test Conditions
A1: A0
A1: A0
DD
DD
First
First
00
01
10
00
01
10
11
11
– 0.2V
– 0.2V
Address
Address
Second
Second
A1: A0
A1: A0
01
00
11
10
01
10
11
00
1
, CE
2
, CE
DD
2t
Min.
CYC
0
)
Address
Address
3
A1: A0
A1: A0
, ADSP, and ADSC must
Third
Third
CY7C1480V33
CY7C1482V33
CY7C1486V33
ZZREC
10
00
01
10
00
01
11
11
2t
2t
Max.
120
CYC
CYC
after the ZZ input
Page 9 of 31
Address
Address
Fourth
A1: A0
Fourth
A1: A0
11
10
01
00
11
00
01
10
Unit
mA
ns
ns
ns
ns
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