CY7C1480V33-167AXC Cypress Semiconductor Corp, CY7C1480V33-167AXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1480V33-167AXC
• Description: CY7C1480V33-167AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480V33-167AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2169; CY7C1480V33-167AXC

Document Number: 38-05283 Rev. *J
Switching Waveforms
Write Cycle Timing
Note
Data Out (Q)
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
ADV
BW
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
t CES
t AS
[21, 22]
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t CL
(continued)
t DS
Single WRITE
D(A1)
t ADH
t DH
A2
D(A2)
DON’T CARE
D(A2 + 1)
t WES
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
ADV suspends burst
X
LOW.
D(A2 + 2)
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
CY7C1480V33
CY7C1482V33
CY7C1486V33
t
ADVS
t WES
Extended BURST WRITE
D(A3 + 1)
t
t WEH
ADVH
Page 23 of 31
D(A3 + 2)
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