CY7C1480V33-167AXC Cypress Semiconductor Corp, CY7C1480V33-167AXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1480V33-167AXC
• Description: CY7C1480V33-167AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480V33-167AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2169; CY7C1480V33-167AXC

Document Number: 38-05283 Rev. *J
Truth Table
The Truth Table for CY7C1480V33, CY7C1482V33, and CY7C1486V33 follows.
Notes
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst
WRITE Cycle,Suspend Burst
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a
“don't care” for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Operation
Add. Used
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
H
H
H
H
H
X
X
X
X
H
X
X
X
L
L
L
L
L
L
L
L
L
1
CE
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
CE
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
3
ZZ ADSP
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
[3, 4, 5, 6, 7]
ADSC
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
H
H
L
L
L
L
L
L
X
. Writes may occur only on subsequent clocks
ADV WRITE OE CLK
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
H
L
L
L
L
L
CY7C1480V33
CY7C1482V33
CY7C1486V33
H
H
H
H
X
X
X
X
X
X
H
X
H
X
X
X
X
L
L
L
L
L
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
Page 10 of 31
X
Tri-State
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
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