CY7C0853V-133BBC Cypress Semiconductor Corp, CY7C0853V-133BBC Datasheet - Page 13

• Manufacturer Part Number: CY7C0853V-133BBC
• Description: IC,SYNC SRAM,256KX36,CMOS,BGA,172PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-133BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 172-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-06059 Rev. *F
TAP Registers
Registers are connected between the TDI and TDO pins and
allow
CY7C0851V/CY7C0852V/CY7C0853V test circuitry. Only
one register can be selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
Instruction Register (IR)
Four-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in Figure 4, the JTAG/BIST
Controller Block Diagram. On power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed in a reset
state, as described in the previous section.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test path.
Bypass Register (BYR)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain devices. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
CY7C0851V/CY7C0852V/CY7C0853V with minimal delay.
The bypass register is set to “0” on the rising edge of TCK
following entry into the Capture-DR state, if the current
instruction causes the bypass register to be in the serial path
between TDI and TDO.
Boundary Scan Register (BSR)
The boundary scan register is connected to all the input and
output pins on the CY7C0851V/CY7C0852V/CY7C0853V,
except the MRST pin. The boundary scan register is loaded
with
CY7C0853V input and output ring when the TAP controller is
in the Capture-DR state. It is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST and SAMPLE/PRELOAD instructions can be
used to capture the contents of the input and output ring.
Identification Register (IDR)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
in the instruction register. The IDCODE is hardwired into the
CY7C0851V/CY7C0852V/CY7C0853V and can be shifted out
when the TAP controller is in the Shift-DR state. The ID
register has a vendor code and other information described in
the Identification Register Definitions table.
TAP Instruction Set
Sixteen different instructions are possible with the four-bit
instruction register. All combinations are listed in Table 5.
Other code combinations are listed as RESERVED and should
not be used.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
the
data
contents
to
be
scanned
of
the
CY7C0851V/CY7C0852V/
into
and
out
PRELIMINARY
of
the
CY7C0851V/CY7C0852V/CY7C0853V
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST allows circuitry external to the CY7C0851V/
CY7C0852V/CY7C0853V package to be tested. Boundary-
scan register cells at output pins are used to apply test stimuli,
while those at input pins capture test results.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register on power-up or whenever
the TAP controller is given a test logic reset state. The
IDCODE value for the CY7C0851V is 0C001069h. The
IDCODE value for the CY7C0852V is 0C002069h. The
IDCODE value for the CY7C0853V is 0C002069h.
High-Z
The High-Z instruction causes the bypass register to be
connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all CY7C0851V/
CY7C0852V/CY7C0853V outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the
CY7C0851V/CY7C0852V/CY7C0853V clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is
no guarantee as to the value that will be captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the CY7C0851V/CY7C0852V/
CY7C0853V signal must be stabilized long enough to meet the
TAP controller's capture set-up plus hold times. Once the data
is captured, it is possible to shift out the data by putting the
TAP into the Shift-DR state. This places the boundary scan
register between the TDI and TDO pins. If the TAP controller
goes into the Update-DR state, the sampled data will be
updated.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected on
a board.
SAMPLE/PRELOAD
CY7C0831V/CY7C0832V
instructions
loaded
Page 13 of 33
into
the