CS4244-CNZ Cirrus Logic Inc, CS4244-CNZ Datasheet - Page 27

• Manufacturer Part Number: CS4244-CNZ
• Description: IC 4 Input / 5 Output CODEC
• Manufacturer: Cirrus Logic Inc

DS900PP2
4.4.2
4.4.3
Master Mode Clock Ratios
As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK
is equal to F
Mode.
The resulting valid master mode clock ratios are shown in
Slave Mode Clock Ratios
In Slave Mode, SCLK and FS/LRCK operate as inputs. The FS/LRCK clock frequency must be equal to
the sample rate, F
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
512x, 256x, 128x, 64x, 48x or 32x F
and
Note:
35. For all cases, the SCLK frequency must be less than or equal to the MCLK frequency.
MCLK/F
SCLK/F
MCLK/F
SCLK/F
MCLK/F
SCLK/F
Table 5
S
S
S
S
S
S
(Note 35)
S
for required clock ratios.
and SCLK is equal to 64x F
S
, and must be synchronously derived from the supplied master clock, MCLK.
MCLK
Table 3. Master Mode Left Justified and I²S Clock Ratios
Table 4. Slave Mode Left Justified and I²S Clock Ratios
Table 5. Slave Mode TDM Clock Ratios
÷1.5
256x, 384x, 512x
÷1
S
Figure 13. Master Mode Clocking
, depending on the desired format and speed mode. Refer to
MCLK Rate Bits
256x
S
PLL active
as shown in
x2
x2
32x, 48x, 64x, 128x
256x, 384x, 512x
256x, 384x, 512x
000
001
010
SSM
Figure
SSM
SSM
64x
Table 3
Speed Mode Bits
13. TDM format is not supported in Master
÷512
÷256
÷8
÷4
512x
512x
below.
00
01
00
01
FS/LRCK
SCLK
128x, 192x, 256x
128x, 192x, 256x
32x, 48x, 64x
DSM
DSM
64x
DSM
256x
256x
CS4244
Table 4
27