CS4244-CNZ Cirrus Logic Inc, CS4244-CNZ Datasheet - Page 25

• Manufacturer Part Number: CS4244-CNZ
• Description: IC 4 Input / 5 Output CODEC
• Manufacturer: Cirrus Logic Inc

DS900PP2
SCL
SDA
The signal timings for a read and write cycle are shown in
fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The
upper 4 bits of the 7-bit address field are fixed at 0010. To communicate with a
field, which is the first byte sent to the
The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address
Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the
register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads
or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from
the
mitted byte.
SDA
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 0010xxx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 0010xxx1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
SCL
START
Figure
CS4244
0
START
0
CHIP ADDRESS (WRITE)
0
1
1
12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
0
0
2
CHIP ADDRESS (WRITE)
0
after each input byte is read, and is input to the
0 1 0
1
3
AD2 AD1 AD0 0
2
4
3
5
AD2 AD1 AD0 0
6
4
7
5
ACK
8
6
9
INCR
7
10 11
ACK
6
8
INCR
5
9
MAP BYTE
Figure 11. Timing, I²C Write
12 13 14 15
Figure 12. Timing, I²C Read
4
10 11
6
3 2 1 0
CS4244
MAP BYTE
5 4
12
13 14 15
3 2 1 0
16
, should match 0010 followed by the settings of the ADx pins.
ACK
STOP
17 18 19
START
16 17 18 19
ACK
0
0
20 21 22 23 24
CHIP ADDRESS (READ)
7
1
CS4244
Figure 11
6
0
DATA
AD2 AD1 AD0 1
1 0
24 25
from the microcontroller after each trans-
ACK
25
26
and
26 27 28
27 28
7
ACK
DATA +1
6
Figure
7
DATA
1 0
0
ACK
12. A Start condition is de-
CS4244
DATA +1
7
7 6
DATA +n
0
1 0
, the chip address
DATA + n
7
ACK
CS4244
STOP
0
CS4244
ACK
NO
STOP
after
25