CS4244-CNZ Cirrus Logic Inc, CS4244-CNZ Datasheet - Page 26

• Manufacturer Part Number: CS4244-CNZ
• Description: IC 4 Input / 5 Output CODEC
• Manufacturer: Cirrus Logic Inc

DS900PP2
4.3.1
4.4
4.4.1
System Clocking
The CS4244 will operate at sampling frequencies from 30 kHz to 100 kHz. This range is divided into two
speed modes as shown in
The serial port clocking must be changed while all PDNx bits are set. If the clocking is changed otherwise,
the device will enter a mute state, see
4.3.1.1
Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudocode above for implementation details.
The CS4244 has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR
is set to ‘0’, MAP will stay constant for successive I²C reads or writes. If INCR is set to ‘1’, MAP will auto-
increment after each byte is read or written, allowing block reads or writes of successive registers.
Master Clock
The ratio of the MCLK frequency to the sample rate must be an integer. The FS/LRCK frequency is equal
to F
are clocked into or out of the device. The
to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode.
trates several standard audio sample rates and the required MCLK and FS/LRCK frequencies.
The CS4244 has an internal fixed ratio PLL. This PLL is activated when the
"Clock & SP Sel." register
these two modes, the PLL will activate to adjust the frequency of the incoming MCLK to ensure that the
internal state machines operate at a nominal 24.576 MHz rate. As is shown in the
sumption
Note:
34. 128x and 192x ratios valid only in Left Justified or I²S formats.
FS/LRCK (kHz)
S
, the frequency at which all of the slots of the TDM stream or channels in Left Justified or I²S formats
Mode
44.1
88.2
table, activation of the PLL will increase the power consumption of the CS4244.
32
48
64
96
Map Increment (INCR)
Single-Speed
Double-Speed
Table
(Note 34)
are set to either 000 or 001, corresponding to 256x or 384x. When in either of
11.2896
12.2880
8.1920
128x
-
-
-
1.
Mode
Table 2. Common Clock Frequencies
Table 1. Speed Modes
Section 4.8 on page
Speed Mode
(Note 34)
12.2880
16.9344
18.4320
192x
DSM
-
-
-
Sampling Frequency
60-100 kHz
30-50 kHz
and
MCLK (MHz)
43.
11.2896
12.2880
16.3840
22.5792
24.5760
8.1920
Master Clock Rate
256x
“MCLK RATE[2:0]” bits in the
12.2880
16.9344
18.4320
384x
-
-
-
bits configure the device
Typical Current Con-
SSM
Table 2
16.3840
22.5792
24.5760
CS4244
512x
-
-
-
illus-
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