CS4207-DNZ Cirrus Logic Inc, CS4207-DNZ Datasheet - Page 131

• Manufacturer Part Number: CS4207-DNZ
• Description: IC Low Pwr,4/6 HD Aud Codec W/HP Amp
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS4207-DNZ

• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 110
• Voltage - Supply, Analog: 2.97 V ~ 5.25 V
• Voltage - Supply, Digital: 2.97 V ~ 5.25 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Package: 48WQFN
• Number Of Channels Per Chip: 16
• Adc/dac Resolution: 24 Bit
• Gain Control: Programmable
• Number Of Dacs: 3
• Number Of Dac Outputs: 2
• Operating Supply Voltage: 1.8|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1798

DS880F1
12:11
10:9
8:6
3:2
5
4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
000b
00b
00b
10b
0b
0b
ADC2 Channel Mode[1:0]: Controls the chan-
nel mapping from the ADC2 output to the HDA
bus.
‘00’b - ADC2 left channel is mapped to HDA left
channel and ADC2 right channel is mapped HDA
right channel (normal mode).
‘01’b - ADC2 left channel is mapped to both HDA
left and right channels. ADC2 right channel is
discarded (mono mode).
‘10’b - ADC2 right channel is mapped to both
HDA left and right channels. ADC2 left channel is
discarded (alternate mono mode).
‘11’b - ADC2 left channel is mapped to HDA right
channel and ADC2 right channel is mapped to
HDA left channel (channel swap mode).
ADC1 Channel Mode[1:0]: Controls the chan-
nel mapping from the ADC1 output to the HDA
bus.
‘00’b - ADC1 left channel is mapped to HDA left
channel and ADC1 right channel is mapped HDA
right channel (normal mode).
‘01’b - ADC1 left channel is mapped to both HDA
left and right channels. ADC1 right channel is
discarded (mono mode).
‘10’b - ADC1 right channel is mapped to both
HDA left and right channels. ADC1 left channel is
discarded (alternate mono mode).
‘11’b - ADC1 left channel is mapped to HDA right
channel and ADC1 right channel is mapped to
HDA left channel (channel swap mode).
Reserved
ADC2 PGA Mode: Sets the topology for the Mic
In 1/Line In 2 PGA.
0 - Fully differential or pseudo-differential mode.
1 - Single-ended mode.
ADC1 PGA Mode: Sets the topology for the Line
In 1/Mic In 2 PGA.
0 - Pseudo-differential mode.
1 - Single-ended mode.
ADC2 SZCMode[1:0]: Same function as ADC1.
See below.
CS4207
131