CS4207-DNZ Cirrus Logic Inc, CS4207-DNZ Datasheet - Page 130

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CS4207-DNZ

Manufacturer Part Number
CS4207-DNZ
Description
IC Low Pwr,4/6 HD Aud Codec W/HP Amp
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS4207-DNZ

Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 3
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
105 / 110
Voltage - Supply, Analog
2.97 V ~ 5.25 V
Voltage - Supply, Digital
2.97 V ~ 5.25 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-QFN
Package
48WQFN
Number Of Channels Per Chip
16
Adc/dac Resolution
24 Bit
Gain Control
Programmable
Number Of Dacs
3
Number Of Dac Outputs
2
Operating Supply Voltage
1.8|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1798

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130
6.15.6.3 ADC Configuration (CIR = 0002h)
Bits
4:3
15
14
13
2
1
0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Type
Default
01b
0b
0b
0b
0b
0b
0b
HOLD[1:0] – Determines how received AES3
audio sample is affected when an receive error
occurs. The errors that affect hold behavior are
parity, bi-phase and confidence. HOLD has no
effect in raw_spdif mode.
00 - hold last audio sample.
01 - replace the current audio sample with all
zeros (mute).
10 - do not change the received audio sample.
11 - reserved
TRUNC – Determines if the audio word length is
set according to the incoming channel status
data as decoded by the AUX[3:0] bits. The
resulting word length in bits is 24 minus
AUX[3:0]. The TRUNC function is valid only on
PCM audio data.
0 – Incoming data is not truncated.
1 – Incoming data is truncated according to the
length specified in the channel status data.
TRUNC has no effect on output data if detected
as being non-audio.
SRC_MUTE – When SRC_MUTE is set to ‘1’,
the SRC will soft-mute when it loses lock and soft
unmute when it regains lock.
0 - Soft mute disabled
1 - Soft mute enabled
Reserved
URG (Unsolicited Response Gating): This bit
allows unsolicited responses to be gated.
0 - Normal propagation of unsolicited responses.
1 - Unsolicited responses are gated if AFG is in
D3.
ADC2 Gain: This bit adjusts the gain of the Mic
In 1/Line In 2 path for the given input topology.
0 - 6 dB gain added (pseudo-differential and sin-
gle-ended mode).
1 - no gain added (fully differential mode).
Note: This bit is OR’ed with the BTL bit in the
Mic In 1/Line In 2 EAPD/BTL Enable
trol.
ADC1 Gain: This bit adjusts the gain of the Line
In 1/Mic In 2 path for the given input topology.
0 - 6 dB gain added (pseudo-differential and sin-
gle-ended mode).
1 - no gain added (not supported - test only).
Description
CS4207
DS880F1
Con-

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