ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 36

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7036
COMPLETE MMR LISTING
In Table 19 to Table 30, addresses are listed in hexadecimal code. Access types include R for read, W for write, and RW for read and write.
Table 19. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0100
0x0104
0x0108
0x010C
1
Table 20. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
0x0234
0x0238
0x023C
0x0560
0x0240
1
Table 21. Timer Address Base = 0xFFFF0300
Address
0x0300
0x0304
0x0308
0x030C
0x0310
0x0314
0x0320
0x0324
0x0328
0x032C
0x0330
Depends on the level on the external interrupt pins (GPIO_0, GPIO_5, GPIO_7, and GPIO_8).
Updated by kernel.
Name
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
FIQSTA
FIQSIG
FIQEN
FIQCLR
Name
SYSMAP0
RSTSTA
RSTCLR
SYSSER0
SYSSER1
SYSALI
SYSCHK
Name
T0LD
T0VAL0
T0VAL1
T0CON
T0CLRI
T0CAP
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
1
1
1
1
1
1
Byte
4
4
4
4
4
4
4
4
4
Byte
1
1
1
4
4
4
4
Byte
2
2
4
4
1
2
4
4
4
1
4
Access
Type
R
R
RW
W
W
R
R
RW
W
Access
Type
RW
RW
W
RW
RW
R
RW
Access
Type
RW
R
R
RW
W
R
RW
R
RW
W
R
Default Value
0x00000000
N/A
0x00000000
N/A
N/A
0x00000000
N/A
0x00000000
N/A
Default Value
N/A
Varies;
depends on
type of reset
N/A
N/A
N/A
N/A
N/A
Default Value
0x0000
0x0000
0x00000000
0x00000000
N/A
0x0000
0x00000000
0xFFFFFFFF
0x01000000
N/A
0x00000000
Active IRQ source. See the Interrupt System section and Table 50.
Current state of all IRQ sources (enabled and disabled). See the Interrupt System
section and Table 50.
Enabled IRQ sources. See the Interrupt System section and Table 50.
MMR to disable IRQ sources. See the Interrupt System section and Table 50.
Software interrupt configuration MMR. See the Programmed Interrupts section
and Table 51.
Active IRQ source. See the Interrupt System section and Table 50.
Current state of all IRQ sources (enabled and disabled). See the Interrupt System
section and Table 50.
Enabled IRQ sources. See the Interrupt System section and Table 50.
Description
Remap control register. See the Remap Operation section and Table 10.
Reset status MMR. See the Reset section and Table 11 and Table 12.
RSTSTA clear MMR. See the Reset section and Table 11 and Table 12.
System Serial Number 0. See the Part Identification section and Table 98 for
details.
System Serial Number 1. See the Part Identification section and Table 99 for
details.
System assembly lot ID. See the Part Identification section for details.
Kernel checksum. See the System Kernel Checksum section.
Description
Timer0 load register. See the Timer0—Lifetime Timer and Timer0 Load Register
sections.
Timer0 Value Register 0. See the Timer0—Lifetime Timer and Timer0 Value
Registers sections.
Timer0 Value Register 1. See the Timer0—Lifetime Timer and Timer0 Value
Registers sections.
Timer0 control MMR. See the Timer0—Lifetime Timer and Timer0 Control
Register sections.
Timer0 interrupt clear register. See the Timer0—Lifetime Timer and Timer0
Load Register sections.
Timer0 capture register. See the Timer0—Lifetime Timer and Timer0 Capture
Register sections.
Timer1 load register. See the Timer1 and Timer1 Load Register sections.
Timer1 value register. See the Timer1 and Timer1 Value Register sections.
Timer1 control MMR. See the Timer1 and Timer1 Control Register sections.
Timer1 interrupt clear register. See the Timer1 and Timer1 Clear Register
sections.
Timer1 capture register. See the Timer1 and Timer1 Capture Register sections.
Description
MMR to disable IRQ sources. See the Interrupt System section and Table 50.
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