ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 32

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7036
ON-CHIP KERNEL
The ADuC7036 features an on-chip kernel resident in the top 2 kB
of the Flash/EE code space. After any reset event, this kernel
copies the factory-calibrated data from the manufacturing data
space into the various on-chip peripherals. The peripherals
calibrated by the kernel are as follows:
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User MMRs that can be modified by the kernel and differ from
their POR default values are as follows:
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The ADuC7036 also features an on-chip LIN downloader. The
derivatives ADuC7036BCPZ and ADuC7036CCPZ use Protocol 4
for programming Flash/EE memory via LIN, where Protocol 6 is
used on derivative ADuC7036DCPZ. The protocols are described
in
AN-946
Flowcharts of the execution of the kernel are shown in Figure 15
and Figure 16. The current revision of the kernel can be derived
from SYSSER1, as described in Table 99.
Application Note AN-881
Power supply monitor (PSM)
Precision oscillator
Low power oscillator
REG_AVDD/REG_DVDD
Low power voltage reference
Normal mode voltage reference
Current ADC (offset and gain)
Voltage/temperature ADC (offset and gain)
R0 to R15
GP0CON/GP2CON
SYSCHK
ADCMDE/ADC0CON
FEE0ADR/FEE0CON/FEE0SIG
HVDAT/HVCON
HVCFG0/HVCFG1
T3LD
(Protocol 6).
(Protocol 4) and
Application Note
Rev. C | Page 32 of 132
After a POR, the watchdog timer is disabled once the kernel
code is exited. For the duration of the kernel execution, the
watchdog timer is active with a timeout period of 500 ms. This
ensures that when an error occurs in the kernel, the ADuC7036
automatically resets. After any other reset, the watchdog timer
maintains user code configuration for the period of the kernel
and is refreshed just prior to kernel exit. A minimum watchdog
period of 30 ms is required to allow correct LIN downloader
operation. If LIN download mode is entered, the watchdog is
periodically refreshed.
Normal kernel execution time, excluding LIN download, is
approximately 5 ms. It is possible to enter and leave LIN
download mode only through a reset.
SRAM is not modified during normal kernel execution; rather,
SRAM is modified during a LIN download kernel execution.
Note that even with NTRST = 0, user code is not executed unless
Address 0x14 contains either 0x27011970 or the checksum of
Page 0, excluding Address 0x14. If Address 0x14 does not contain
this information, user code is not executed and LIN download
mode is entered. During kernel execution, JTAG access is disabled.
With NTRST = 1, user code is always executed.
The ADuC7036DCPZ allows for user-defined bootloader
functionality. The bootloader can be of any size up to 30 kB but
must be located at the top of user flash. The top-most three
words must be the following:
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The kernel uses the values at these addresses in determining if
the bootloader is valid.
Note that this bootloader checksum is the sum of all half words
from the value pointed to by 0x977F8 up to the half word at
0x977F6.
Address 0x977FC must contain the checksum of the
bootloader.
Address 0x977F8 must contain the lowest address of the
bootloader block.
Address 0x977F4 must contain the entry point of the
bootloader code.