ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 30

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7036
Block 0, Flash/EE Memory Protection Registers
Name: FEE0HID and FEE0PRO
Address: 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO)
Default Value: 0xFFFFFFFF (for FEE0HID) and 0x00000000 (for FEE0PRO)
Access: Read/write access
Function: These registers are written by user code to configure the protection of the Flash/EE memory.
Table 16. FEE0HID and FEE0PRO MMR Bit Designations
Bit
31
30
29
28 to 0
1
Block 1, Flash/EE Memory Protection Registers
Name: FEE1HID and FEE1PRO
Address: 0xFFFF0EA0 (for FEE1HID) and 0xFFFF0E9C (for FEE1PRO)
Default Value: 0xFFFFFFFF (for FEE1HID) and 0x00000000 (for FEE1PRO)
Access: Read/write access
Function: These registers are written by user code to configure the protection of the Flash/EE memory.
Table 17. FEE1HID and FEE1PRO MMR Bit Designations
Bit
31
30
29 to 0
The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.
Description
Read protection bit.
Set by user code to allow reading of the 64 kB Flash/EE block code via JTAG read access.
Cleared by user code to read protect the 64 kB Flash/EE block code via JTAG read access.
Write protection bit. Write protects eight pages. Each page consists of 512 bytes.
Set by user code to allow writes to Page 120 to Page 127 of the 64 kB Flash/EE code memory.
Cleared by user code to write protect Page 120 to Page 127 of the 64 kB Flash/EE code memory.
Write protection bits.
Set by user code to allow writes to Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit write protects four pages, and
each page consists of 512 bytes.
Cleared by user code to write protect Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit write protects two pages,
and each page consists of 512 bytes.
Description
Read protection bit.
Set by user code to allow reading the 32 kB Flash/EE block code via JTAG read access.
Cleared by user code to protect the 32 kB Flash/EE block code via JTAG read access.
Write protection bit.
Set by user code to allow writes to Page 59.
Cleared by user code to write protect Page 59.
Write protection bit.
Set by user code to allow writes to Page 58.
Cleared by user code to write protect Page 58.
Write protection bits.
Set by user code to allow writes to Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two pages, and
each page consists of 512 bytes.
Cleared by user code to write protect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two pages, and
each page consists of 512 bytes.
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