ADUC7023BCP6Z62IRL Analog Devices Inc, ADUC7023BCP6Z62IRL Datasheet - Page 86

• Manufacturer Part Number: ADUC7023BCP6Z62IRL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCP6Z62IRL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12 x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T2CLRI to avoid a
watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8 + X6 + X5 + X + 1
shown in Figure 45.
The initial value or seed is written to T2CLRI before entering watchdog mode. After entering watchdog mode, a write to T2CLRI must
match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the
expected state, a reset is immediately generated, even if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the properties of the polynomial. The value 0x00 is always guaranteed to force
an immediate reset. The value of the LFSR cannot be read; it must be tracked/generated in software.
An example of a sequence follows:
1.
2.
3.
4.
5.
Enter initial seed, 0xAA, in T2CLRI before starting Timer2 in watchdog mode.
Enter 0xAA in T2CLRI; Timer2 is reloaded.
Enter 0x37 in T2CLRI; Timer2 is reloaded.
Enter 0x6E in T2CLRI; Timer2 is reloaded.
Enter 0x66. 0xDC was expected; the watchdog resets the chip.
CLOCK
Q
7
D
Q
6
D
Q
5
D
Rev. B | Page 86 of 96
Figure 45. 8-Bit LFSR
Q
4
D
Q
3
D
Q
2
D
Q
1
D
Q
0
D