ADUC7023BCP6Z62IRL Analog Devices Inc, ADUC7023BCP6Z62IRL Datasheet - Page 14

• Manufacturer Part Number: ADUC7023BCP6Z62IRL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCP6Z62IRL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12 x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
P0.4/IRQ0/SCL0/PLAI[0]/CONV
Table 9. Pin Function Descriptions
40-LFCSP
0
36
37
38
39
32
31
30
8
2
3
4
P0.5/SDA0/PLAI[1]/COMP
P2.0/ADC12/PWM4/PLAI[7]
P1.4/ADC10/PLAO[3]
Pin No.
NOTES
1. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE
THAT MUST BE LEFT UNCONNECTED.
32-LFCSP
0
28
29
30
31
N/A
N/A
N/A
N/A
2
3
4
GND
DAC1
DAC2
DAC3
START
DAC0
AV
OUT
REF
DD
10
1
2
3
4
5
6
7
8
9
ADuC7023
(Not to Scale)
Figure 7.
TOP VIEW
Mnemonic
Exposed Paddle
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
P2.4/ADC9/PLAI[10]
P2.3/ADC8/PLAO[7]
P2.2/ADC7/SYNC/PLAO[6]
P2.0/ADC12/PWM4/PLAI[7]
GND
DAC0
DAC1
REF
30 P2.2/ADC7/SYNC/PLAO[6]
29 P1.5/ADC6/PWM
28 P0.3/PLAO[9]/TCK
27 P0.2/PLAO[8]/TDI
26 P0.1/PLAI[9]/TDO
25 P0.0/nTRST/ADC
24 TMS
23 RTCK
22 XCLKO
21 XCLKI
TRIPINPUT
BUSY
PLAI[8]/BM
/PLAO[4]
Rev. B | Page 14 of 96
Description
Exposed Pad. The LFCSP_VQ only has an exposed paddle that must be left
unconnected.
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
General-Purpose Input and Output Port 2.4/ADC Single-Ended or
Differential Analog Input/Programmable Logic Array Input Element 10.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
General-Purpose Input and Output Port 2.3/ADC Single-Ended or
Differential Analog Input 8/Programmable Logic Array Output Element 7.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, pull-up resistor should be
disabled manually.
General-Purpose Input and Output Port 2.2/ADC Single-Ended or
Differential Analog Input 7/PWM Sync /Programmable Logic Array Output
Element 6. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, pull-up resistor should
be disabled manually.
General-Purpose Input and Output Port 2.0/ADC Single-Ended or
Differential Analog Input 12/PWM Output 4/Programmable Logic Array
Input Element 7. By default, this pin is configured as a digital input with a
weak pull-up resistor enabled. When used as an ADC input, it is not
possible to disable the internal pull-up resister. This means that this pin
has a higher leakage current value than other analog input pins.
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from DGND.
DAC0 Voltage Output or ADC Input.
DAC1 Voltage Output or ADC Input.
P0.4/IRQ0/SCL0/PLAI[0]/CONV
P0.5/SDA0/PLAI[1]/COMP
NOTES
1. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE
THAT MUST BE LEFT UNCONNECTED.
GND
DAC0
DAC1
DAC2
DAC3
START
AV
OUT
REF
DD
1
2
3
4
5
6
7
8
ADuC7023
(Not to Scale)
Figure 8.
TOP VIEW
24
23
22
21
20
19
18
17
P0.3/PLAO[9]/TCK
P0.2/PLAO[8]/TDI
P0.1/PLAI[9]/TDO
P0.0/nTRST/ADC
TMS
RTCK
XCLKO
XCLKI
BUSY
/PLAI[8]/BM