ADUC7023BCP6Z62IRL Analog Devices Inc, ADUC7023BCP6Z62IRL Datasheet - Page 68

• Manufacturer Part Number: ADUC7023BCP6Z62IRL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCP6Z62IRL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12 x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
Bit
0
PLACLK Register
Name:
Address:
Default value:
Access:
Function:
Table 77. PLACLK MMR Bit Descriptions
Bit
31 to 7
6 to 4
2 to 0
3
Value
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
PLACLK
0xFFFF0B40
0x00
Read/write
PLACLK is the clock selection for the flip-
flops. The maximum frequency when using
the GPIO pins as the clock input for the PLA
blocks is 41.78 MHz.
Value
Description
Reserved.
Clock source selection.
GPIO clock on P0.5.
GPIO clock on P1.1.
GPIO clock on P1.6.
HCLK.
External 32.768 kHz crystal.
Timer1 overflow.
UCLK.
Internal 32,768 oscillator.
Reserved.
Clock source selection.
GPIO clock on P0.5.
GPIO clock on P1.1.
GPIO clock on P1.6.
HCLK.
External 32.768 kHz crystal.
Timer1 overflow.
UCLK.
Internal 32,768 oscillator.
Description
Mux 4 control.
This bit is set by the user to bypass the flip-flop.
This bit is cleared by the user to select the flip-flop (cleared by default).
Rev. B | Page 68 of 96
PLAIRQ Register
Name:
Address:
Default value:
Access:
Function:
Table 78. PLAIRQ MMR Bit Descriptions
Bit
31 to 13
12
11 to 8
7 to 5
4
3 to 0
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
PLAIRQ
0xFFFF0B44
0x00000000
Read/write
PLAIRQ enables IRQ0 and/or IRQ1 and
selects the source of the IRQ.
Description
Reserved.
PLA IRQ1 enable bit.
PLA Element 0.
PLA Element 1.
PLA Element 2.
PLA Element 3.
PLA Element 4.
PLA Element 5.
PLA Element 6.
PLA Element 7.
PLA Element 8.
PLA Element 9.
PLA Element 10.
PLA Element 11.
PLA Element 12.
PLA Element 13.
PLA Element 14.
PLA Element 15.
Reserved.
PLA IRQ0 enable bit.
This bit is set by the user to enable IRQ0
output from PLA.
This bit is cleared by the user to disable
IRQ0 output from PLA.
PLA IRQ0 source.
PLA Element 0.
PLA Element 1.
PLA Element 2.
PLA Element 3.
PLA Element 4.
PLA Element 5.
PLA Element 6.
PLA Element 7.
Reserved.