ADUC7023BCP6Z62IRL Analog Devices Inc, ADUC7023BCP6Z62IRL Datasheet - Page 59

• Manufacturer Part Number: ADUC7023BCP6Z62IRL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCP6Z62IRL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12 x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
The I
I
I
Name:
Address:
Default value:
Access:
Function:
Table 64. I2CxMCON MMR Bit Designations
Bit
15 to 9
8
7
6
5
4
3
2
1
0
2
2
2
C Master Registers
C REGISTERS
C Master Control Registers, I2CxMCON
2
C peripheral interfaces consists of a number of MMRs. These are described in the following section.
Name
I2CMCENI
I2CNACKENI
I2CALENI
I2CMTENI
I2CMRENI
I2CMSEN
I2CILEN
I2CBD
I2CMEN
I2C0MCON, I2C1MCON
0xFFFF0800, 0xFFFF0900
0x0000, 0x0000
Read/write
These 16-bit MMRs configure the I
Description
Reserved. These bits are reserved and should not be written to.
I
This bit is set to enable an interrupt on detecting a stop condition on the I
This bit clears this interrupt source.
I
This bit is set to enable interrupts when the I
This bit clears this interrupt source.
I
This bit is set to enable interrupts when the I
This bit clears this interrupt source.
I
This bit is set to enable interrupts when the I
This bit clears this interrupt source.
I
This bit is set to enable interrupts when the I
This bit is cleared by the user to disable interrupts when the I
I
This bit is set to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low
until I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
This bit is cleared to disable clock stretching.
I
This bit is set to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to
their respective input signals.
This bit is cleared by the user to disable loopback mode.
I
This bit is set to allow the device to compete for control of the bus even if another device is currently driving a
start condition.
This bit is cleared to back off until the I
I
This bit is set by the user to enable I
This bit is cleared to disable I
2
2
2
2
2
2
2
2
2
C transmission complete interrupt enable bit.
C no acknowledge received interrupt enable bit.
C arbitration lost interrupt enable bit.
C transmit interrupt enable bit.
C receive interrupt enable bit.
C master SCL stretch enable bit.
C internal loopback enable bit.
C master backoff disable bit.
C master enable bit.
2
2
C master mode.
C peripheral in master mode.
2
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C master mode.
2
C bus becomes free.
2
2
2
2
C master receives a no acknowledge.
C master has lost in trying to gain control of the I
C master has transmitted a byte.
C master receives data.
2
C master is receiving data.
2
C bus.
2
C bus.
ADuC7023