ADSP-21369BSWZ-2A Analog Devices Inc, ADSP-21369BSWZ-2A Datasheet - Page 43

333 MHz, Shared Memory,S/PDIF EPAD PBfr

ADSP-21369BSWZ-2A

Manufacturer Part Number
ADSP-21369BSWZ-2A
Description
333 MHz, Shared Memory,S/PDIF EPAD PBfr
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet

Specifications of ADSP-21369BSWZ-2A

Interface
DAI, DPI
Clock Rate
333MHz
Non-volatile Memory
ROM (768 kB)
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-LQFP
Device Core Size
32/40Bit
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
333MHz
Mips
333
Device Input Clock Speed
333MHz
Ram Size
256KB
Program Memory Size
768KB
Operating Supply Voltage (typ)
1.2/3.3V
Operating Supply Voltage (min)
1.14/3.13V
Operating Supply Voltage (max)
1.26/3.47V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
LQFP EP
Package
208LQFP EP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
333 MHz
Device Million Instructions Per Second
333 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21369BSWZ-2A
Manufacturer:
Analog Devices Inc
Quantity:
10 000
S/PDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table
routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 37. S/PDIF Transmitter Input Data Timing
1
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 38. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Parameter
TxCLK Frequency for TxCLK = 384 × FS
TxCLK Frequency for TxCLK = 256 × FS
Frame Rate (FS)
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
SISCLKW
SISCLK
SITXCLKW
SITXCLK
1
1
1
1
37. Input signals SCLK, frame sync (FS), and SDATA are
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
Transmit Clock Width
Transmit Clock Period
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(TxCLK)
(SCLK)
(FS)
t
SITXCLKW
Figure 33. S/PDIF Transmitter Input Timing
SAMPLE EDGE
Rev. E | Page 43 of 60 | July 2009
t
SISCLKW
t
SISFS
Min
t
SISD
t
SISCLK
t
SITXCLK
ADSP-21367/ADSP-21368/ADSP-21369
Min
3
3
3
3
36
80
9
20
Max
Oversampling Ratio × FS <= 1/t
49.2
192.0
t
t
SIHFS
SIHD
Max
SITXCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
MHz
kHz

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