ADSP-21369BSWZ-2A Analog Devices Inc, ADSP-21369BSWZ-2A Datasheet - Page 34

• Manufacturer Part Number: ADSP-21369BSWZ-2A
• Description: 333 MHz, Shared Memory,S/PDIF EPAD PBfr
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369BSWZ-2A

• Interface: DAI, DPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 333MHz
• Mips: 333
• Device Input Clock Speed: 333MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: LQFP EP
• Package: 208LQFP EP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 333 MHz
• Device Million Instructions Per Second: 333 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21367/ADSP-21368/ADSP-21369
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 28. Serial Ports—External Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
1
1
1
2
1
2
2
2
FS Setup Before SCLK
(Externally Generated FS in Either
Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in Either
Transmit or Receive Mode)
Receive Data Setup Before Receive
SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
FS Delay After SCLK
(Internally Generated FS in Either
Transmit or Receive Mode)
FS Hold After SCLK
(Internally Generated FS in Either
Transmit or Receive Mode)
Transmit Data Delay After Transmit
SCLK
Transmit Data Hold After Transmit
SCLK
Min
2.5
2.5
1.9
2.5
(t
t
2
2
PCLK
PCLK
× 4
× 4) ÷ 2 – 0.5
Rev. E | Page 34 of 60 | July 2009
400 MHz
366 MHz
350 MHz
Max
10.25
7.8
Serial port signals SCLK, frame sync (FS), data channel A, data
channel B are routed to the DAI_P20–1 pins using the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20–1 pins.
Min
2.5
2.5
2.0
2.5
t
2
2
(t
PCLK
PCLK
× 4
× 4) ÷ 2 – 0.5
333 MHz
Max
10.25
9.6
Min
2.5
2.5
2.5
2.5
(t
t
2
2
PCLK
PCLK
× 4
× 4) ÷ 2 – 0.5
266 MHz
Max
10.25
9.8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns