AD9985KSTZ-140 Analog Devices Inc, AD9985KSTZ-140 Datasheet - Page 21

• Manufacturer Part Number: AD9985KSTZ-140
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9985KSTZ-140

• Applications: Video
• Interface: Serial Port
• Voltage - Supply: 2.2 V ~ 3.45 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MODE CONTROL 1
0E
Table 13. Hsync Input Polarity Override Settings
Override Bit
0
1
0E
Table 14. Hsync Input Polarity Settings
HSPOL
0
1
The power-up default value is HSPOL = 1.
0E
Table 15. Hsync Output Polarity Settings
Setting
0
1
0E
7
This register is used to override the internal circuitry
that determines the polarity of the Hsync signal going
into the PLL.
The default for Hsync polarity override is 0 (polarity
determined by chip).
6
A bit that must be set to indicate the polarity of the
Hsync signal that is applied to the PLL Hsync input.
Active Low means the leading edge of the Hsync pulse
is negative going. All timing is based on the leading
edge of Hsync, which is the falling edge. The rising
edge has no effect.
Active high is inverted from the traditional Hsync,
with a positive-going pulse. This means that timing
will be based on the leading edge of Hsync, which is
now the rising edge.
The device will operate if this bit is set incorrectly, but
the internally generated clamp position, as established
by Clamp Placement (Register 05H), will not be
placed as expected, which may generate clamping
errors.
5
This bit determines the polarity of the Hsync output
and the SOG output. Table 15 shows the effect of this
option. SYNC indicates the logic state of the sync
pulse.
The default setting for this register is 0.
4
This bit is used to override the automatic Hsync
selection, To override, set this bit to Logic 1. When
overriding, the active Hsync is set via Bit 3 in this
register.
Hsync Output Polarity
Hsync Input Polarity Override
HSPOL Hsync Input Polarity
Active Hsync Override
SYNC
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
Function
Hsync Polarity Determined by Chip
Hsync Polarity Determined by User
Function
Active Low
Active High
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Table 16. Active Hsync Override Settings
Override
0
1
0E
Table 17. Active HSYNC Select Settings
Select
0
1
0E
Table 18. Vsync Output Invert Settings
Setting
0
1
0E
Table 19. Active Vsync Override Settings
Override
0
1
0E
Table 20. Active Vsync Select Settings
Select
0
1
The default for this register is 0.
3
This bit is used under two conditions. It is used to
select the active Hsync when the override bit is set
(Bit 4). Alternately, it is used to determine the active
Hsync when not overriding but both Hsyncs are
detected.
The default for this register is 0.
2
This bit inverts the polarity of the Vsync output.
Table 18 shows the effect of this option.
The default setting for this register is 0.
1
This bit is used to override the automatic Vsync
selection. To override, set this bit to Logic 1. When
overriding, the active interface is set via Bit 0 in this
register.
The default for this register is 0.
0
This bit is used to select the active Vsync when the
override bit is set (Bit 1).
The default for this register is 0.
Result
HSYNC Input
Sync-on-Green Input
Vsync Output
Invert
No Invert
Result
Vsync Input
Sync Separator Output
Result
Autodetermines the Active Interface
Override, Bit 3 Determines the Active Interface
Result
Autodetermines the Active Vsync
Override, Bit 0 Determines the Active Vsync
Active Hsync Select
Vsync Output Invert
Active Vsync Override
Active Vsync Select
AD9985