AD9985KSTZ-140 Analog Devices Inc, AD9985KSTZ-140 Datasheet - Page 18

• Manufacturer Part Number: AD9985KSTZ-140
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9985KSTZ-140

• Applications: Video
• Interface: Serial Port
• Voltage - Supply: 2.2 V ~ 3.45 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9985
Hex
Address
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
*The AD9985 updates the PLL divide ratio only when the LSBs are written to (Register 02H).
Write and
Read or
Read Only
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
Bits
7:0
7:0
7:0
7:0
7:2
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7
6
5:2
1:0
7:0
1
0
Default
Value
*****0**
******0*
*******0
00100000
00000000
00000000
111111**
******1*
*******1
00000100
00000100
00000100
00010001
0*******
*0******
**1001**
******10
0000****
Register Name
Sync Separator
Threshold
Pre-Coast
Post-Coast
Sync Detect
Reserved
Output Formats
Reserved
Test Register
Test Register
Test Register
Red Target Code
Green Target
Code
Blue Target
Code
Auto Offset
Enable
Hold Auto Offset
Update Mode
Reserved
Reserved
Test Register
Rev. 0 | Page 18 of 32
Reserved for future use.
Reserved for future use.
Must be written to 11h for proper operation.
Changes the update rate of the auto offset.
Function
Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
Sync Separator Threshold. Sets how many internal 5 MHz clock periods
the sync separator will count to before toggling high or low. This
should be set to some number greater than the maximum Hsync or
equalization pulsewidth.
Pre-Coast. Sets the number of Hsync periods that Coast becomes
active prior to Vsync.
Post-Coast. Sets the number of Hsync periods that Coast stays active
following Vsync.
Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the
analog interface; otherwise it is set to Logic 0.
Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync is
being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from Sync-on-
Green.)
Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the analog
interface; otherwise it is set to Logic 0.
Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync is
being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from Sync
Separator.)
Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present on
the Green video input; otherwise it is set to 0.
Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bits [7:2] Reserved for future use. Must be written to 111111 for proper
operation.
Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1=
4:4:4 mode)
Bit 0 – Must be set to 0 for proper operation.
Reserved for future use.
Target Code for Auto Offset Operation.
Target Code for Auto Offset Operation.
Target Code for Auto Offset Operation.
Enables the auto offset circuitry.
Holds the offset output of the auto offset at the current value.
Must be written to 9 for proper operation.
Must be set to default value.