AD9775BSVZ Analog Devices Inc, AD9775BSVZ Datasheet - Page 45

• Manufacturer Part Number: AD9775BSVZ
• Description: IC,D/A CONVERTER,DUAL,14-BIT,CMOS,TQFP,80PIN
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9775BSVZ

• Settling Time: 11ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Number Of Channels: 2
• Resolution: 14b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3.1V
• Single Supply Voltage (max): 3.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9775-EBZ - BOARD EVALUATION FOR AD9775
• Lead Free Status / Rohs Status: Compliant

Figure 102. Test Configuration for AD9775 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,
Figure 101. Test Configuration for AD9775 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate,
ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
NOTES
1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25
NOTES
1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT
PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE
FOR MORE INFORMATION.
DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
INPUT CLOCK
INPUT CLOCK
JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
JUMPER CONFIGURATION FOR ONE-PORT MODE PLL ON
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
AWG2021
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
AWG2021
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
DG2020
DG2020
OR
OR
SOLDERED/IN
SOLDERED/IN
LECROY
PULSE
GENERATOR
LECROY
PULSE
GENERATOR
×
×
×
×
×
40-PIN RIBBON CABLE
×
×
×
×
×
UNSOLDERED/OUT
UNSOLDERED/OUT
Rev. E | Page 45 of 56
TRIG
TRIG
INP
INP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
DAC1, DB13–DB0
DAC2, DB13–DB0
DAC1, DB13–DB0
DAC2, DB13–DB0
ONEPORTCLK
DATACLK
SIGNAL GENERATOR
SIGNAL GENERATOR
CLK+/CLK–
CLK+/CLK–
AD9775
AD9775
AD9775